c8e2eebe77
[Bridges] Fix instnace naming
2020-05-05 20:27:53 +00:00
e39aac3a4c
[FPGATop] Croak on host-memory ID truncation
2020-05-04 22:03:40 +00:00
7ca584e498
Provide a mechanism to constrain host DRAM ID use
2020-05-02 18:49:15 +00:00
dcf1b311b8
Increase ID width to maximum supported size; update zynq configs
2020-05-02 04:35:34 +00:00
4599101f4f
misc. cleanup and doc. clarification
2020-04-28 20:47:12 -07:00
6832d719be
update documentation | consolidate makefile changes
2020-04-27 20:19:01 -07:00
8dfb4e253a
[firesim] remove un-needed generator utils
2020-04-27 23:36:52 +00:00
df4514d1ae
Merge remote-tracking branch 'origin/dev' into fromajosim
2020-04-22 00:01:32 -07:00
f82e115c66
Rocket Chip Bump 4/2020. THIS COMMIT WILL NOT COMPILE; BUMP CY
...
Two major changes:
Abstract reset and async reset support introduced -> change Async reset
handling
Old generator utilties removed -> copy them into FireSim for
now
More Nasti <-> AXI4 hacks
Update onExprt in AsyncReset coerce
Drop gemmini's host frequency
Bump SBT version and provide a missing plugin for FSimAsTop
Regenerate AGFIs
2020-04-18 05:14:41 +00:00
7c121894e9
Merge branch 'dev', remote-tracking branch 'origin' into diplomatic-widgets
2020-04-10 22:24:18 +00:00
1949930a4a
[Bridges] Fix indentation for lazy module impls
2020-04-10 22:22:26 +00:00
d0f2139a3c
[bridges] Ensure DRAM allocation does not exceed total capacity
2020-04-10 21:45:18 +00:00
019a15c4bb
[bridges] Sort DRAM-requesting bridges using size _and_ name
2020-04-08 07:44:39 +00:00
b1ff973a25
[bridges] Relax Pow2 constaint on DRAM regions
2020-04-07 12:02:25 -07:00
a4f0a18c0a
[platform] Make F1Shim ID allocation wrap correctly
2020-04-06 23:22:21 -07:00
d95036c227
Make shims lazy modules; Fix runtime conf generation
2020-04-06 22:23:13 -07:00
7aec556ea4
[Platform] Split out PlatformShim; Add a small readme
2020-04-06 22:23:13 -07:00
17927595b7
[platform] Cleanup debug printfs in F1 Shim
2020-04-06 22:23:13 -07:00
83e0c01792
Emit only fixed-width integer types in the generated header
2020-04-06 22:23:13 -07:00
69cd89784e
[Bridge] Make bridges diplomatic; add generalized DRAM allocation
...
This commit affects to major changes:
1) It makes BridgeModules diplomatic. To port existing bridges it should
simply be a matter of taking the body of the existing bridge module and
wrapping in a BridgeModuleImp class instance.
2) Leveraging (1), it introduces intelligent FPGA DRAM-allocation for
bridge Modules. Bridges requiring FPGA DRAM should mixin UsesHostDRAM
to their LazyModule definitions.
2020-04-06 22:23:13 -07:00
db1915b19b
Fix synthesized_prints SW driver
2020-04-03 15:10:28 -07:00
29fd2d3505
Merge remote-tracking branch 'origin/dev' into fromajosim
2020-03-31 11:37:18 -07:00
91c20c9c56
[trigger] Workaround constProp(?) issue in trigger wiring
2020-03-24 15:31:50 -07:00
30426accbe
Order bridge annotations by their order in the clock token vec
2020-03-24 15:30:58 -07:00
552a9764a1
A small fix to output-clock referencing
2020-03-24 10:11:39 -07:00
fc9e4366e3
FindClockSourcesSpec typos
2020-03-24 00:17:10 -07:00
b6e1169c41
[tracerv] Pipeclean new trigger system
2020-03-24 00:17:10 -07:00
f49d6f6df1
[channels] Use zero as the initial token value in PipeChannel
...
Previously we just took whatever was on in.bits. I don't anyone was using this "feature".
2020-03-24 00:17:10 -07:00
438a86b1ec
Keep target clock outputs around as wires for convenience
2020-03-23 22:56:28 +00:00
ddd331bf69
[passes] Add some FindClockSource test
2020-03-21 23:08:22 -07:00
00a41e9cfc
[config] Remove defunct midas.TraceTrigger
2020-03-21 23:07:16 -07:00
8e1b06f8e0
Add code comments to key multiclock sources
2020-03-21 16:35:02 -07:00
2c5d7e82a0
[trigger] Re-implement TracerV trigger using new system
2020-03-21 00:50:48 -07:00
1137ae3859
[passes] Move wiring transform into TriggerWiring
2020-03-21 00:28:48 -07:00
dc85bbb821
[autocounter] Provide a note about frequency selection
2020-03-21 00:28:18 -07:00
ff35d03dbb
Fix order of arguments to LogicNode in ClockSourceFinder
2020-03-20 23:46:25 +00:00
20266d7313
[passtests] Clean up imports
2020-03-20 16:12:46 -07:00
d822d951cc
[passes] Pull in FIRRTL testutils files until 3.2
2020-03-20 16:05:34 -07:00
4616b37119
Make clock-tracing component of FindClockSources a library
2020-03-20 19:27:15 +00:00
6c0a483b9d
Fix FindClockSources
2020-03-20 16:27:20 +00:00
25dc4aab9b
[tracerv] Pass clock-domain info to tracerV, update +args
2020-03-18 16:58:14 -07:00
69c9ad11ad
[print] Use new clock info class
2020-03-18 16:58:14 -07:00
68d68db089
[autocounter] Pass clock domain info to autocountert
2020-03-18 16:58:14 -07:00
d4c351d93d
[bridges] Add a small utility class for clock domain info
2020-03-18 16:58:14 -07:00
d3bd8b2ae3
Cleanup some code after FindClockSources change
2020-03-18 21:23:15 +00:00
5f8fc97b42
Update sim/midas/src/main/scala/midas/passes/BridgeTopWiring.scala
...
Co-Authored-By: Albert Magyar <albert.magyar@gmail.com>
2020-03-18 14:05:08 -07:00
d5e9fff265
Update sim/midas/src/main/scala/midas/passes/BridgeTopWiring.scala
...
Co-Authored-By: Albert Magyar <albert.magyar@gmail.com>
2020-03-18 14:04:51 -07:00
18eb990064
Update sim/midas/src/main/scala/midas/passes/BridgeTopWiring.scala
...
Co-Authored-By: Albert Magyar <albert.magyar@gmail.com>
2020-03-18 14:04:02 -07:00
e13b33200b
Remove commented-out transforms from Midas compiler
2020-03-18 13:55:36 -07:00
652e84f8c9
Skip over 'passthru' instances in FindClockSources
2020-03-18 20:12:55 +00:00
88e77d07f9
Merge remote-tracking branch 'origin/dev' into multiclock
2020-03-18 09:23:05 -07:00
53c8c9b693
Merge remote-tracking branch 'origin/dev' into fromajosim
2020-03-17 20:52:28 -07:00
def75eb18e
bugfix for 1 stream
2020-03-17 13:06:48 -07:00
fff18549bc
[print] Clean up some comments
2020-03-17 10:16:10 -07:00
55a45fc9f9
update makefiles to properly build driver | properly invoke simulator
2020-03-15 02:23:19 +00:00
afef8c13f5
[midas] add makefrag changes | add firesim_top.cc instantiation
2020-03-13 10:59:59 -07:00
6edc8a20dc
[printf] Use clock-domain info in print bridge & driver
2020-03-12 22:02:42 -07:00
0f3405cc3a
[Bridges] Provide target clock info through host Parameters
2020-03-12 22:01:08 -07:00
e13a236af0
[ClockBridge] Update API to accept RationalClock case classes
2020-03-12 21:58:44 -07:00
5cac9aaa75
[trigger] Mask events with reset if available
2020-03-12 09:42:29 -07:00
320f6360f1
[gg] Implement multi-clock compatible wiring
2020-03-11 15:33:07 -07:00
ab9b0c22e5
[rtlutils] Add a utility for generating reset-less registers
2020-03-11 15:33:07 -07:00
d0613c8d07
[fame] Add Neq to RTLUtils
2020-03-11 03:57:41 +00:00
2214c7bbc4
[midasexamples] Add a TriggerWiringModule integration test
2020-03-11 03:56:23 +00:00
7aae84d40f
[targetutils] Add Chisel API for triggering
2020-03-11 03:56:23 +00:00
6a55e6e931
[gg] Delete obselete ChannelizeTargetIO pass
2020-03-11 03:56:23 +00:00
42f6373009
[printf] Provide default printf filenames that don't collide
2020-03-11 03:56:23 +00:00
9f9705762a
[make] remove un-needed VCS flag
2020-03-09 17:50:32 -07:00
370230cf78
[make] re-add space for VCS
2020-03-09 16:07:51 -07:00
771f5532d8
Merge remote-tracking branch 'origin/dev' into firesim-blackbox-integration-cleanup
2020-03-07 21:45:38 +00:00
3271801d70
[make] move target specific flags to firesim makefrag
2020-03-06 22:23:09 +00:00
13bf4c1482
Remove unused CDC code
2020-03-05 20:43:35 -08:00
218a9f22c3
[AutoCounter] Include only common regnames in generated struct
2020-03-05 13:28:50 -08:00
fb458fe45f
[AutoCounter] Simplify the initialization process
...
It had weird behavior under multiclock
2020-03-05 13:10:54 -08:00
6ee1c04ea8
Remove an errant printf
2020-03-05 11:29:59 -08:00
1e938c62cc
[Bridge] Allow for registers to be excluded from struct
2020-03-05 11:29:27 -08:00
644fde8a67
[AutoCounter] DontTouch all signals
2020-03-05 11:28:02 -08:00
23b87ae9f8
[bridges] Disambiguate between printf bridge drivers
2020-03-03 17:09:39 -08:00
23b80238aa
dramsim stuff moved to chipyard/testchipip
2020-03-02 20:55:17 -08:00
32eb41f289
[WIP] Albert revert me! Disable FAME5 transform
2020-03-01 23:00:02 -08:00
00e167e363
[targetutils] Provide assert failure message for RTRenamer.exact
2020-03-01 22:57:25 -08:00
ccfbf5a3be
[gg] Overhaul AutoCounter for Multiclock support
...
In order to reuse BridgeTopWiring, i dropped the old the scheme of
instantiating the bridges as modules. As part of these changes I made
some other modifications / optimizations.
- AutoCounter Annotations now include a reset and clock ReferenceTarget
- PerfCounter apply uses the implicit clock and reset if available
- The bridge-based implementation no longer generates counters in the
target
- The Bool representing the event is wired to the bridge; and the
counter is instantiated there
- Saves on token queueing; 64 bit registers were already present in
the Bridge
- Bridge resource optimizations
- Smaller counter-sample queue (more queueing shouldn't doesn't improve
simulation performance under a fixed sample frequency).
- Fewer MMIO registers; simpler dequeue handshake logic saves a MMIO
transaction
2020-03-01 22:46:10 -08:00
4ef36824c0
[passes] Port printf synthesis to BridgeTopWiring
2020-03-01 13:44:40 -08:00
0b1ed5a691
[passes] BridgeTopWiring fixes
2020-03-01 13:42:47 -08:00
5a54dcf36c
[make] fix condition in ariane switch
2020-02-28 19:14:28 -08:00
5648fc0254
[verilator] bump to 4.028
2020-02-28 17:42:57 -08:00
8393a2370b
[make] cleanly swap between ariane and other flags
2020-02-28 16:56:36 -08:00
ee884b731e
[misc] cleanup makefiles | remove extra build recipe | revert docs on TracerV
2020-02-28 10:59:23 -08:00
8ed0c33100
[tests] Add a smoke test for BridgeTopWiring
2020-02-27 14:27:41 -08:00
b919213258
[passes] Add a BridgeTopWiring; tracks an associated clock
2020-02-27 14:26:17 -08:00
f00d681aa9
[make] add verilog generation to vcs/verilator dependency list | update vcs/verilator flags | extra sed'ing on verilog out
2020-02-25 16:26:55 -08:00
1d44793591
Merge remote-tracking branch 'origin/dev' into multiclock
...
Known issues:
- Clock analysis pass under printf synthesis has different behavior
- Async Reset seems to break FAME5 transform
- Autocounter nees to be ported
2020-02-13 12:16:33 -08:00
bf725a743f
[gg] Add a comment about CB counter widths
2020-02-12 18:28:35 -08:00
11074e435a
[gg] Move cycle counters to clock Bridge. Update FMR
2020-02-12 18:06:28 -08:00
a6accd5b5e
Update sim/midas/src/main/verilog/BUFGCE.v
...
Co-Authored-By: Albert Magyar <albert.magyar@gmail.com>
2020-02-11 23:00:36 -05:00
dd5dead368
[gg] Fix ram optimizations under clock-gating F1 xform
2020-02-11 18:05:07 -08:00
cd559aa5d8
The finest bugfix in my time at Berkeley
2020-02-07 01:45:34 +00:00
619192e3f9
Only use Verilator-friendly clock gate in Verilator sim
2020-02-07 01:45:34 +00:00
874e775507
Explicitly keep target clock gated while under reset
2020-02-07 01:45:34 +00:00
09af1a6d5a
Remove simReset
...
This was mostly unused and confusing. We're going to rely on reprogramming
for the foreseeable future as a means to deterministically reset the
simulator
2020-02-07 01:45:34 +00:00
6ae4f052eb
[synthPrintf] Use topWiringPrefix to prevent name collisions
2020-01-30 20:09:27 +00:00
82e05f05f6
Merge pull request #475 from firesim/parallel-verilator-compilation
...
[makefrag] Parallelize verilator-based ML-simulator compilation
2020-01-26 23:29:13 -08:00
c1b61cf1b4
[makefrag] Parallelize verilator-based ML-simulator compilation
2020-01-25 00:41:52 +00:00
3e4aab98e0
[docs] Add a UARTBridge Walkthrough
2020-01-22 12:48:05 -08:00
ef734c235f
Enable MuxingMultiThreader by default
2020-01-12 15:22:01 -08:00
8ce7935b39
Use small rocketchip ShiftQueues in channels
2020-01-12 15:21:26 -08:00
119d473964
Fix FAME5Info; fix write enables in MuxingMultiThreader
2020-01-12 15:20:51 -08:00
451956ef35
Add MuxedMultiThreader that produces mux-based microarchitecture
2020-01-12 02:55:55 -08:00
12a28d1c21
Fix handling of sync-read mems in FAME5 transform
2020-01-10 03:18:30 -08:00
522646cfb9
Merge branch 'multiclock' of github.com:firesim/firesim into multiclock
2020-01-09 02:00:12 -08:00
c9cc460979
WIP on FAME5, works for TwoAdder design
2020-01-09 02:00:04 -08:00
1b2824d6a8
[gg] Handle unconnected clock ports in FindClockSources
2020-01-08 12:01:55 -08:00
bfda4e71ba
[gg] Remove unneeded default annotations in FAMEDefaults
2019-12-19 17:24:19 -08:00
6cfdc30aee
[gg] Make FindClockSources a Transform; multiclock print synthesis
2019-12-17 23:32:44 -08:00
1cc01360b9
[autocounter] Workaround the host port problem
2019-12-17 15:33:38 -08:00
5f5c33f641
chisel bump modifications
2019-12-17 01:38:02 +00:00
1cde84538a
Allow multiple single-clock models to compose with a multi-clock hub model
2019-12-16 17:32:01 -08:00
1afabf56e8
Rename host clock from clock to hostClock
2019-12-16 17:28:19 -08:00
6c6c209589
[gg] Fix assert pass under no assertions
2019-12-16 15:36:31 -08:00
200b0e81c8
[manager] Do not copy over an asserts file
2019-12-16 11:30:49 -08:00
ebf082502c
[gg] Bring up multiclock assertion synthesis
2019-12-16 11:30:31 -08:00
a400d1ccff
Merge remote-tracking branch 'origin/dev' into triggers-counters-integration-clean
2019-12-16 11:23:46 -08:00
9621a15a00
[gg] Add a temporary utility to find clock sources
2019-12-10 16:31:53 -08:00
f28c1b1ba0
Merge in dev; bump chipyard; fix FSimAsTop
2019-12-10 22:48:11 +00:00
40b07d974f
address PR review comments from Albert
2019-12-10 00:37:25 -08:00
0ee151cf3e
Fix all projects for chisel 3.2.0
2019-12-09 08:47:42 -08:00
7ef7fe369f
move autocounter to midas, and address other PR comments
2019-12-06 23:13:33 -08:00
f7c3a97901
Fixes for chisel 3.2.0
2019-12-06 15:51:20 -08:00
dcabed76ae
AutoCounter transform and bridge for automatic perf counters
2019-12-02 22:14:24 -08:00
f1c21620fa
More info in assertion message
2019-12-02 22:10:38 -08:00
ff54c0f606
generate AddressMap for all widgets
2019-12-02 22:09:48 -08:00
538debe35b
Add TracerV trigger
2019-12-02 22:07:48 -08:00
74cd34baaf
[gg] Make SimulationMapping robust against target name collisions
2019-11-25 18:12:52 -08:00
2643c32d53
[gg] Bring up multiclock assertion synthesis; reenable AS in examples
2019-11-23 20:13:50 -08:00
1aaca790d1
The finest bugfix in my time at Berkeley
2019-11-22 15:47:21 -08:00
d22b57b770
Only use Verilator-friendly clock gate in Verilator sim
2019-11-20 15:02:35 -08:00
5b086b2ec4
[gg] Properly emit reverse decoupled channel annotations
2019-11-20 00:26:26 -08:00
26e326698b
[gg] Print out channels that are missing a clock in FAME1 xform
2019-11-20 00:25:43 -08:00
c2c436147c
[gg] Check that a single clock bridge instance is extracted
2019-11-19 23:55:57 -08:00
040610098d
[gg] Magyar-ify EnsureNoTargetIO
2019-11-19 23:34:47 -08:00
8aeed3484a
[gg] Also check for clock ports in EnsureNoTargetIO.scala
2019-11-19 22:58:32 -08:00
a9b0899cf1
[midasexamples] Bring up a simple test of multiclock
2019-11-18 11:28:32 -08:00
0ffbb5d149
Add raw module multithreader
2019-11-15 19:21:18 -08:00
61e7ee0481
[GG] Instantiate clock token generator; pipe clean sim wrapper
2019-11-14 23:03:59 -08:00
b1d99e7dd7
[GG] Make ClockBridgeAnnotation serializable
2019-11-14 22:43:47 -08:00
3937721552
[GG] Fix SimWrapper/Bridge related issues
2019-11-14 22:00:29 -08:00
562e162a8d
Delete DontTouch annos when transforming FAME models
2019-11-14 21:52:08 -08:00
83ab93c7d9
Makes it to SimWrapper generator
2019-11-14 11:05:30 -08:00
dbbe9d657c
Add logic to deal with clock channel connections
2019-11-13 14:27:21 -08:00
d95c3d2e83
More work on propagating channel clocks
2019-11-11 18:28:24 -08:00
9d1b4f81a0
[gg] Move Compiler.scala -> passes/Compilers.scala
2019-11-11 15:29:21 -08:00
a090464263
[gg] Remove defunct AddedTargetIOAnnotation; use bridges
2019-11-11 15:29:21 -08:00
ff905338d2
[gg] Stop passing around targetIO
2019-11-11 15:29:20 -08:00
051e5bb91d
[gg] Remove legacy Compiler object; use phase only
2019-11-11 15:29:20 -08:00
b07dbb7342
[gg] Remove platform mapping; change platform selection
2019-11-11 15:29:20 -08:00
854096f1f3
WIP on multiclock FAME transform
2019-11-10 21:14:52 -08:00
e151aa56b1
Make clock gating unconditional for now
2019-11-10 13:34:16 -08:00
4b69ba1390
Move patient SSM transformers to separate file
2019-11-10 13:32:26 -08:00
266dd7ac23
[gg] Rewrite irrevocable assertions in terms of leaf values
2019-11-05 14:23:34 -08:00
099e9db408
[gg] Put token irrevocability assertions on a switch
2019-11-04 16:10:48 -08:00
2fd68cfd80
Update token irrevocability assertion generation
2019-11-04 10:57:20 -08:00
014711691b
[WIP] Emit ClockChannel annotations using FCCA for now
2019-11-01 16:51:55 -07:00
dffab9fb13
[Multiclock] Add clock fields to Bridges; update FCCAs to target them
2019-11-01 11:29:58 -07:00
dd724e217b
Match FCCAs with or without clocks
2019-10-30 17:59:52 -07:00
ab4d4a04ac
[WIP] [WIP] Rational clock bridge
2019-10-30 17:23:29 -07:00
ae6c22115f
Construct FCCAs using new factory methods
2019-10-30 17:21:16 -07:00
2bc44adeaa
Add clock field to FCCA, add ClockChannel info type
2019-10-30 16:07:05 -07:00
c8f5af8e50
Inline the MIDAS submodule
2019-10-18 18:03:19 +00:00
d2c3552c35
Bump MIDAS
2019-10-12 05:03:08 +00:00
d5eaddb06d
Update runtime config generation to use a new stage
2019-10-10 02:18:05 +00:00
a1f3a927a9
Rename Endpoint -> Bridge
2019-10-06 03:35:03 +00:00
9bd6679ea8
Serializable Endpoints & Golden Gate as a Stage
2019-10-04 22:43:46 -07:00
4c1a3aa212
Update build recipes to reflect new config organization
2019-10-04 18:28:19 +00:00
9ca73689af
Merge remote-tracking branch 'origin/dev' into midas2-endpoint-rework
2019-09-19 09:42:50 -07:00
9edf0b86a7
Bump MIDAS to let IsEndpoint mix into BaseModules
2019-09-17 11:49:53 -07:00
d794bbb5e9
Bump MIDAS and update FASEDtests
2019-09-17 11:40:38 -07:00
6e56ad2bed
Bump MIDAS; HostPort moved into widgets
2019-09-13 00:32:11 -07:00
a61d42b1c8
Bump chipyard and midas to dev
2019-09-13 00:21:37 +00:00
3b8cb231c8
Bump MIDAS; FASEDEndpoint use in AXI4 Fuzzer
2019-09-07 17:47:43 -07:00
d24f8cc6d9
Update endpoint definitions
2019-09-06 12:14:39 -07:00
17a95ef2d4
Bump MIDAS; note token backpressure hack ( #335 )
2019-08-29 04:20:31 +00:00
d6a802135a
Merge remote-tracking branch 'origin/midas2' into midas2-endpoint-rework
2019-08-19 11:17:36 -07:00
35b0be7c7f
Merge remote-tracking branch 'origin/dev' into midas2
2019-08-16 19:19:09 +00:00
e5feeda548
Bump MIDAS for variable renaming
2019-07-24 21:46:23 +00:00
341a538b6f
Merge 'origin/master' into dev for blkdev fix; bump midas
2019-07-23 23:19:34 +00:00
895fb37d2d
Add +vcs+initmem+0; add the vcs args to the .d-derived MLSim targets
2019-07-23 15:41:38 -07:00
a3d48a43a9
Bump midas for channel name changes
2019-07-23 21:59:58 +00:00
c7784c60d2
Merge remote-tracking branch 'origin/dev' into midas2
2019-07-23 21:10:30 +00:00
78fdff25af
Update MACRO names :(
2019-07-12 19:50:55 -07:00
0aa7ff93c7
Bring up Printf Synthesis
2019-07-12 16:44:20 -07:00
448eae5f4f
Bring up assertion synthesis
2019-07-12 16:00:49 -07:00
be6bc69abd
Update MemModelKey to use Endpoint; bring up FASEDtests
2019-07-12 14:50:15 -07:00
765e2ab144
Update all MIDAS examples to use BlackBox endpoints
2019-07-12 11:02:54 -07:00
1c7f6a99ea
have midas support memory channels with different address widths
2019-07-11 15:14:11 -07:00
62ea9e5fc2
Update endpoint IO definitions; include tReset in HostPorts
2019-07-10 22:31:37 -07:00
8718224132
[WIP] Black box-based endpoint rework; GCD simulates
2019-07-09 17:46:43 -07:00
7f8152e511
Bump MIDAS to dev
2019-06-28 23:51:58 +00:00
40ca9c71ac
Merge remote-tracking branch 'origin/dev' into firesim-as-a-library
2019-06-28 04:57:46 +00:00
c91aba2252
Bump MIDAS for new RV channel implementation
2019-06-27 17:55:07 -07:00
5c2aaa3f64
Merge submodule dev branches into master; bump
2019-06-26 22:41:23 +00:00
29b905c2b3
Initialize channels with tokens to improve FMR
2019-06-24 11:53:30 -07:00
503d2135c5
Fix TracerV test
2019-06-21 17:18:33 -07:00
6147071b1f
[M2] Readd a lost config, and bump
2019-06-20 23:46:33 +00:00
2d2cb5db73
Bump MIDAS
2019-06-20 16:41:35 +00:00
0b3bba7324
Get RiscSRAM working again
2019-06-20 01:12:54 +00:00
c11eb9f1ee
Pull in firesim dev; most of the midas examples work
2019-06-19 23:34:23 +00:00
40965603a0
Bump firesim, WIP
2019-06-19 22:09:02 +00:00
d3c4930a2c
ICCAD submission
2019-06-19 19:23:05 +00:00
0205a85d18
Major reorganization to enable FireSim-as-a-library
2019-05-29 00:48:03 +00:00
b8d1ea3f6f
Add a finish method to all endpoints and call it
2019-05-24 17:33:55 +00:00
db94bdc244
Bump RC once more; fix diplomatic trace handling
2019-05-16 19:07:06 +00:00
33086134fe
WIPCITY
2019-05-11 07:19:54 +00:00
e8e9fd1ee4
Bump MIDAS and publish AGFIs
2019-04-25 21:35:33 +00:00
5da102e56c
Add support for runtime configurable MSHRs in FASED LLC models
2019-04-24 19:38:04 +00:00
42353ab8d5
Get ram-replacement working for RiscSRAM
2019-03-29 00:20:18 +00:00
70ba9dd058
Bump midas
2019-03-26 17:17:45 -07:00
9ac4065e49
Actually bump midas
2019-03-26 23:56:42 +00:00
12e9d10a47
Enable port annotation generation
2019-03-26 19:22:45 +00:00
88bc426ff5
bump to midas master
2019-02-24 16:43:44 -08:00
1d7f5607c5
Bump midas
2019-02-18 04:00:42 +00:00
773a29e66c
Update more names, purge software memory model
2019-02-17 14:21:10 -08:00
6beec9f4bd
Update references to FASED; Add scalatests
2019-02-16 22:25:53 -08:00
71c04a5c96
Bump MIDAS
2019-02-13 22:36:09 +00:00
cd77c1bd93
Bump MIDAS for RVChannel non-determinism fixes
2019-02-11 05:09:19 +00:00
1f298f5a18
Bump midas to dev
2019-02-07 01:54:33 +00:00
dc1537ad50
[print] Update plusargs to synthesized printf driver
2019-02-04 15:37:21 -08:00
22a70aa26f
Bump MIDAS for verilator lint rule fixes
2019-01-22 21:56:35 +00:00
76d38433e0
Add ram model annotations to boom and rocket RFs; add tests
2019-01-22 19:50:56 +00:00
c6ad5ff011
Bump MIDAS to head of dev
2019-01-20 01:33:18 +00:00
f04c282ebf
Bump MIDAS
2019-01-19 04:49:46 +00:00
4c24c4175f
Bump midas and update docs for improved FpgaDebug annotator
2019-01-19 00:05:38 +00:00
fcce6d4a17
[print] Update printfile plusarg to be consistent
2019-01-17 01:29:38 +00:00
1511828f01
Bump midas
2019-01-15 17:32:19 +00:00
196140105f
Remove branch-specific FIRRTL features, bump FIRRTL to master
2019-01-03 20:50:19 -08:00
3df039b6ea
Bump midas for TopWiringAnno fix
2018-12-28 15:24:11 +00:00
5595dbb785
[print] Add cases for the bugs Albert encountered
2018-12-20 16:26:21 +00:00
ce909c1fbe
Bump midas
2018-12-15 16:42:58 -08:00
c50dd9ebfc
[Print] Enable token compression
2018-12-15 16:31:55 -08:00
1073f6b759
[print] Add a midasexample that packs narrow printf tokens
2018-12-15 14:06:47 -08:00
e7825e7962
[print] Diff logs in scalatest
2018-12-15 12:14:29 -08:00
30507d49f6
[print] Add a (currently failing) test to diff output
2018-12-14 08:41:06 +00:00
0c01768611
Bump midas
2018-12-14 08:38:27 +00:00
af6b3f6bf1
[print] Bring up printSynth in rocket
2018-12-14 08:37:38 +00:00
70f093fd8c
[Driver] Properly invoke endpoint dtors
2018-12-14 08:37:02 +00:00
b64b87f5fb
[Print] Support synthesized printfs that exceed DMA width
2018-12-14 08:35:43 +00:00
886c987210
[midasexamples] Update initialization and teardown of print widget
2018-12-14 08:35:11 +00:00
249ab27082
[midasexamples] Add print plusargs
2018-12-14 08:34:16 +00:00
0dc7f528ee
[midasexamples] Properly instantiate print endpoint
2018-12-14 08:33:12 +00:00
981fddbde0
[WIP] Add a failing PrintModule midas example
2018-12-14 08:23:14 +00:00
3ee77b8fac
Bump midas
2018-12-12 22:22:05 +00:00
David Biancolin