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Fix order of arguments to LogicNode in ClockSourceFinder

This commit is contained in:
Albert Magyar 2020-03-20 23:46:25 +00:00
parent 20266d7313
commit ff35d03dbb
1 changed files with 2 additions and 1 deletions
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3
sim/midas/src/main/scala/midas/passes/ClockSourceFinder.scala
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@ -41,7 +41,8 @@ class ClockSourceFinder(state: CircuitState) {
def findRootDriver(queryTarget: ReferenceTarget): Option[ReferenceTarget] = {
require(queryTarget.component.isEmpty)
def getPortDriver(rT: ReferenceTarget): Option[ReferenceTarget] = {
val node = LogicNode(rT.ref, rT.component.collectFirst { case Field(f) => f })
val portOption = rT.component.collectFirst { case Field(f) => f }
val node = portOption.map(p => LogicNode(p, Some(rT.ref))).getOrElse(LogicNode(rT.ref))
val (inst, module) = rT.path.lastOption.getOrElse((Instance(rT.module), OfModule(rT.module)))
val drivingCone = connectivity(module.value).reachableFrom(node)
val drivingPorts = (drivingCone + node) & inputClockNodeSets(module.value)