[rtlutils] Add a utility for generating reset-less registers

2020-03-11 15:30:18 -07:00 · 2020-03-11 15:30:18 -07:00 · ab9b0c22e5
parent d0613c8d07
commit ab9b0c22e5
1 changed files with 8 additions and 0 deletions
--- a/sim/midas/src/main/scala/midas/passes/fame/RTLUtils.scala
+++ b/sim/midas/src/main/scala/midas/passes/fame/RTLUtils.scala
@ -68,3 +68,11 @@ object Or extends BinaryBooleanOp {
 object Neq extends BinaryBooleanOp {
  val op = PrimOps.Neq
 }
+
+/** Generates a DefRegister with no reset, relying instead on FPGA programming
+  * to preset the register to 0
+  */
+object RegZeroPreset {
+  def apply(info: Info, name: String, tpe: Type, clock: Expression): DefRegister =
+    DefRegister(info, name, tpe, clock, zero, WRef(name))
+}