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Bring up assertion synthesis

This commit is contained in:
David Biancolin 2019-07-12 16:00:49 -07:00
parent be6bc69abd
commit 448eae5f4f
4 changed files with 8 additions and 8 deletions
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2
sim/midas

@ -1 +1 @@
Subproject commit aee6d33a41cca65a9ebaa10245b9f5d443ecada8
Subproject commit 292aab91a84970a8a78e4892a9db4c9502afafb8

8
sim/src/main/cc/firesim/firesim_top.cc
View File

@ -330,10 +330,10 @@ uint64_t host_mem_offset = -0x80000000LL;
// There can only be one instance of assert and print widgets as their IO is
// uniquely generated by a FIRRTL transform
#ifdef ASSERTIONWIDGET_struct_guard
#ifdef ASSERTIONWIDGET_0_PRESENT
ASSERTIONWIDGET_0_substruct_create;
add_endpoint(new synthesized_assertions_t(this, ASSERTIONWIDGET_0_substruct));
#ifdef MIDASASSERTS_struct_guard
#ifdef MIDASASSERTS_PRESENT
MIDASASSERTS_substruct_create;
add_endpoint(new synthesized_assertions_t(this, MIDASASSERTS_substruct));
#endif
#endif

4
sim/src/main/cc/midasexamples/AssertModule.h
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@ -8,8 +8,8 @@ class AssertModule_t: virtual simif_t
public:
synthesized_assertions_t * assert_endpoint;
AssertModule_t(int argc, char** argv) {
ASSERTIONWIDGET_0_substruct_create;
assert_endpoint = new synthesized_assertions_t(this, ASSERTIONWIDGET_0_substruct);
MIDASASSERTS_substruct_create;
assert_endpoint = new synthesized_assertions_t(this, MIDASASSERTS_substruct);
};
void run() {
int assertions_thrown = 0;

2
sim/src/main/scala/midasexamples/Config.scala
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@ -11,7 +11,7 @@ class NoConfig extends Config(Parameters.empty)
// This is incomplete and must be mixed into a complete platform config
class DefaultF1Config extends Config(new Config((site, here, up) => {
case firesim.util.DesiredHostFrequency => 75
case SynthAsserts => false
case SynthAsserts => true
case midas.GenerateMultiCycleRamModels => true
case SynthPrints => false
}) ++ new Config(new firesim.firesim.WithDefaultMemModel ++ new midas.F1Config))