[gg] Make FindClockSources a Transform; multiclock print synthesis
This commit is contained in:
David Biancolin
parent
1cde84538a
commit
6cfdc30aee
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@ -187,7 +187,7 @@ private[passes] class AssertPass(
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// Step 4: Associate each assertion with a source clock
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val postWiredState = state.copy(circuit = c.copy(modules = mods), form = MidForm)
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val loweredState = Seq(new ResolveAndCheck, new HighFirrtlToMiddleFirrtl, new MiddleFirrtlToLowFirrtl).foldLeft(postWiredState)((state, xform) => xform.transform(state))
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val clockMapping = FindClockSources(loweredState, mInfo.allClocks)
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val clockMapping = FindClockSources.analyze(loweredState, mInfo.allClocks)
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val rootClocks = mInfo.allClocks.map(clockMapping)
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// For each clock in clock channel, list associated assert indices
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@ -9,8 +9,25 @@ import firrtl.annotations.TargetToken.{OfModule, Instance}
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import firrtl.graph.{DiGraph}
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import firrtl.analyses.InstanceGraph
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object FindClockSources {
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private def getSourceClock(moduleGraphs: Map[String,DiGraph[LogicNode]])
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import midas.passes.fame.RTRenamer
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case class FindClockSourceAnnotation(
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target: ReferenceTarget,
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originalTarget: Option[ReferenceTarget] = None) extends Annotation {
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require(target.module == target.circuit, s"Queried leaf clock ${target} must provide an absolute instance path")
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def update(renames: RenameMap): Seq[FindClockSourceAnnotation] =
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Seq(this.copy(RTRenamer.exact(renames)(target), originalTarget.orElse(Some(target))))
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}
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case class ClockSourceAnnotation(queryTarget: ReferenceTarget, source: ReferenceTarget) extends Annotation {
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def update(renames: RenameMap): Seq[ClockSourceAnnotation] = Seq(this.copy(queryTarget, RTRenamer.exact(renames)(source)))
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}
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object FindClockSources extends firrtl.Transform {
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def inputForm = LowForm
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def outputForm = LowForm
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private def getSourceClock(moduleGraphs: Map[String,DiGraph[LogicNode]],
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moduleDeps: Map[String, Map[String,String]])
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(rT: ReferenceTarget): ReferenceTarget = {
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val modulePath = (OfModule(rT.module) +: rT.path.map(_._2)).reverse
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val instancePath = (None +: rT.path.map(tuple => Some(tuple._1))).reverse
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@ -20,17 +37,22 @@ object FindClockSources {
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val (instOpt, module) :: restOfPath = path
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val mGraph = moduleGraphs(module.value)
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val source = if (mGraph.findSinks(currentNode)) currentNode else mGraph.reachableFrom(currentNode).head
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require(source.inst == None, "TODO: Handle clocks that may traverse a submodule hierarchy")
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restOfPath match {
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case Nil => source
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case _ => walkModule(LogicNode(source.name, instOpt.map(_.value)), restOfPath)
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(restOfPath, source) match {
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// Source is a port on the top level module -> we're done
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case (Nil, LogicNode(_, None, _)) => source
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// Source is a port on an instance in our current module; prepend it to the path and recurse
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case (_, LogicNode(port, Some(instName),_)) =>
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val childModule = moduleDeps(module.value)(instName)
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walkModule(LogicNode(port), (Some(Instance(instName)), OfModule(childModule)) +: path)
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// Source is a port but we are not yet at the top; recurse into parent module
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case (nonEmptyPath, _) => walkModule(LogicNode(source.name, instOpt.map(_.value)), nonEmptyPath)
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}
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}
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val sourceClock = walkModule(LogicNode(rT.ref), instancePath.zip(modulePath))
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rT.moduleTarget.ref(sourceClock.name)
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}
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def apply(state: CircuitState, queryTargets: Seq[ReferenceTarget]): Map[ReferenceTarget, ReferenceTarget] = {
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def analyze(state: CircuitState, queryTargets: Seq[ReferenceTarget]): Map[ReferenceTarget, ReferenceTarget] = {
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queryTargets.foreach(t => {
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require(t.component == Nil)
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require(t.module == t.circuit, s"Queried leaf clock ${t} must provide an absolute instance path")
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@ -52,6 +74,18 @@ object FindClockSources {
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val simplifiedSubgraph = subgraph.simplify((clockPorts ++ instClockNodes ++ queriedNodes).toSet)
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module -> simplifiedSubgraph
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}
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(queryTargets.map(qT => qT -> getSourceClock(clockConnectivity.toMap)(qT))).toMap
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(queryTargets.map(qT => qT -> getSourceClock(clockConnectivity.toMap, moduleDeps)(qT))).toMap
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}
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def execute(state: CircuitState): CircuitState = {
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val queryAnnotations = state.annotations.collect({ case anno: FindClockSourceAnnotation => anno })
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val sourceMappings = analyze(state, queryAnnotations.map(_.target))
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val clockSourceAnnotations = queryAnnotations.map(qAnno =>
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ClockSourceAnnotation(qAnno.originalTarget.getOrElse(qAnno.target), sourceMappings(qAnno.target)))
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val prunedAnnos = state.annotations.flatMap({
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case _: FindClockSourceAnnotation => None
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case o => Some(o)
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})
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state.copy(annotations = clockSourceAnnotations ++ prunedAnnos)
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}
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}
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@ -29,11 +29,10 @@ private[passes] class PrintSynthesis(dir: File)(implicit p: Parameters) extends
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private val printMods = new mutable.HashSet[ModuleTarget]()
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private val formatStringMap = new mutable.HashMap[ReferenceTarget, String]()
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// Generates a bundle to aggregate
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// Generates a bundle containing a print's clock, enable, and argument fields
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def genPrintBundleType(print: Print): Type = BundleType(Seq(
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Field("enable", Default, BoolType)) ++
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print.args.zipWithIndex.map({ case (arg, idx) => Field(s"args_${idx}", Default, arg.tpe) })
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)
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Field("clock", Default, ClockType), Field("enable", Default, BoolType)) ++
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print.args.zipWithIndex.map({ case (arg, idx) => Field(s"args_${idx}", Default, arg.tpe) }))
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def getPrintName(p: Print, anno: SynthPrintfAnnotation, ns: Namespace): String = {
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// If the user provided a name in the annotation use it; otherwise use the source locator
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@ -57,17 +56,17 @@ private[passes] class PrintSynthesis(dir: File)(implicit p: Parameters) extends
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// Takes a single printPort and emits an FCCA for each field
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def genFCCAsFromPort(mT: ModuleTarget, p: Port): Seq[FAMEChannelConnectionAnnotation] = {
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println(p)
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p.tpe match {
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case BundleType(fields) =>
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fields.map(field =>
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FAMEChannelConnectionAnnotation.implicitlyClockedSource(
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case BundleType(clockField :: dataFields) =>
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dataFields.map(field =>
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FAMEChannelConnectionAnnotation.source(
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p.name + "_" + field.name,
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WireChannel,
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clock = Some(mT.ref(p.name).field(clockField.name)),
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Seq(mT.ref(p.name).field(field.name))
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)
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)
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case other => Seq()
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case other => ???
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}
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}
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@ -75,7 +74,10 @@ private[passes] class PrintSynthesis(dir: File)(implicit p: Parameters) extends
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require(state.annotations.collect({ case t: TopWiringAnnotation => t }).isEmpty,
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"CircuitState cannot have existing TopWiring annotations before PrintSynthesis.")
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val c = state.circuit
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def mTarget(m: Module): ModuleTarget = ModuleTarget(c.main, m.name)
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def portRT(p: Port): ReferenceTarget = ModuleTarget(c.main, c.main).ref(p.name)
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def portClockRT(p: Port): ReferenceTarget = portRT(p).field("clock")
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val modToAnnos = printfAnnos.groupBy(_.mod)
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@ -92,12 +94,13 @@ private[passes] class PrintSynthesis(dir: File)(implicit p: Parameters) extends
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def onStmt(annos: Seq[SynthPrintfAnnotation], modNamespace: Namespace)
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(s: Statement): Statement = s.map(onStmt(annos, modNamespace)) match {
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case p @ Print(_,format,args,_,en) if annos.exists(_.format == format.string) =>
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case p @ Print(_,format,args,clk,en) if annos.exists(_.format == format.string) =>
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val associatedAnno = annos.find(_.format == format.string).get
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val printName = getPrintName(p, associatedAnno, modNamespace)
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// Generate an aggregate with all of our arguments; this will be wired out
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val wire = DefWire(NoInfo, printName, genPrintBundleType(p))
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val enableConnect = Connect(NoInfo, wsub(WRef(wire), s"enable"), en)
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val clockConnect = Connect(NoInfo, wsub(WRef(wire), "clock"), clk)
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val enableConnect = Connect(NoInfo, wsub(WRef(wire), "enable"), en)
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val argumentConnects = (p.args.zipWithIndex).map({ case (arg, idx) =>
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Connect(NoInfo,
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wsub(WRef(wire), s"args_${idx}"),
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@ -106,15 +109,16 @@ private[passes] class PrintSynthesis(dir: File)(implicit p: Parameters) extends
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val printBundleTarget = associatedAnno.mod.ref(printName)
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topWiringAnnos += TopWiringAnnotation(printBundleTarget, topWiringPrefix)
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formatStringMap(printBundleTarget) = format.serialize
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Block(Seq(p, wire, enableConnect) ++ argumentConnects)
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Block(Seq(p, wire, clockConnect, enableConnect) ++ argumentConnects)
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case s => s
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}
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// Step 1: Find and replace printfs with stubs
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val processedCircuit = c.map(onModule)
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// Step 2: Wire out print stubs to top level module
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val wiredState = (new TopWiringTransform).execute(state.copy(
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circuit = processedCircuit,
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annotations = state.annotations ++ topWiringAnnos))
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val topModule = wiredState.circuit.modules.find(_.name == wiredState.circuit.main).get
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val portMap: Map[String, Port] = topModule.ports.map(port => port.name -> port).toMap
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val addedPrintPorts = topLevelOutputs.map({ case ((cname,_,_,path,prefix),_) =>
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@ -124,31 +128,39 @@ private[passes] class PrintSynthesis(dir: File)(implicit p: Parameters) extends
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(port, formatString)
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})
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// Step 3: Using each printf bundle clock, group them into separate clock domains
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val findClockSourceAnnos = addedPrintPorts.map({ case (port, _) => FindClockSourceAnnotation(portClockRT(port)) })
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val stateToAnalyze = wiredState.copy(annotations = findClockSourceAnnos ++ wiredState.annotations)
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val loweredState = Seq(new ResolveAndCheck,
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new HighFirrtlToMiddleFirrtl,
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new MiddleFirrtlToLowFirrtl,
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FindClockSources).foldLeft(stateToAnalyze)((state, xform) => xform.transform(state))
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val clockMapping = loweredState.annotations.collect({ case ClockSourceAnnotation(qT, source) => qT -> source }).toMap
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val groupedPrints = addedPrintPorts.groupBy({ case (port, _) => clockMapping(portClockRT(port)) })
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println(s"[MIDAS] total # of prints synthesized: ${addedPrintPorts.size}")
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val printRecordAnno = addedPrintPorts match {
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case Nil => Seq()
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case ports => {
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// TODO: Generate sensible channel annotations once we can aggregate wire channels
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val portName = topWiringPrefix.stripSuffix("_")
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val mT = ModuleTarget(c.main, c.main)
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val portRT = mT.ref(portName)
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val fccaAnnos = ports.flatMap({ case (port, _) => genFCCAsFromPort(mT, port) })
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val bridgeAnno = BridgeIOAnnotation(
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target = portRT,
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widget = (p: Parameters) => new PrintBridgeModule(topWiringPrefix, addedPrintPorts)(p),
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channelNames = fccaAnnos.map(_.globalName)
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)
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bridgeAnno +: fccaAnnos
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}
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// Step 4: Generate FCCAs and Bridge Annotations for each clock domain
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val printRecordAnnos = for ((clockRT, ports) <- groupedPrints) yield {
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// TODO: Generate sensible channel annotations once we can aggregate wire channels
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val portName = topWiringPrefix.stripSuffix("_")
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val mT = ModuleTarget(c.main, c.main)
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val portRT = mT.ref(portName)
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val fccaAnnos = ports.flatMap({ case (port, _) => genFCCAsFromPort(mT, port) })
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val bridgeAnno = BridgeIOAnnotation(
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target = portRT,
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widget = (p: Parameters) => new PrintBridgeModule(topWiringPrefix, ports)(p),
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channelNames = fccaAnnos.map(_.globalName)
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)
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bridgeAnno +: fccaAnnos
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}
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// Remove added TopWiringAnnotations to prevent being reconsumed by a downstream pass
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val cleanedAnnotations = wiredState.annotations.flatMap({
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case TopWiringAnnotation(_,_) => None
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case otherAnno => Some(otherAnno)
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})
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wiredState.copy(annotations = cleanedAnnotations ++ printRecordAnno)
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wiredState.copy(annotations = cleanedAnnotations ++ printRecordAnnos.toSeq.flatten)
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}
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def execute(state: CircuitState): CircuitState = {
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@ -17,11 +17,13 @@ class PrintRecord(portType: firrtl.ir.BundleType, val formatString: String) exte
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def regenLeafType(tpe: firrtl.ir.Type): Data = tpe match {
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case firrtl.ir.UIntType(width: firrtl.ir.IntWidth) => UInt(width.width.toInt.W)
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case firrtl.ir.SIntType(width: firrtl.ir.IntWidth) => SInt(width.width.toInt.W)
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case firrtl.ir.SIntType(width: firrtl.ir.IntWidth) => SInt(width.width.toInt.W)
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case badType => throw new RuntimeException(s"Unexpected type in PrintBundle: ${badType}")
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}
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val args: Seq[(String, Data)] = portType.fields.collect({
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case firrtl.ir.Field(name, _, tpe) if name != "enable" => (name -> Output(regenLeafType(tpe)))
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case firrtl.ir.Field(name, _, tpe) if name != "enable" && name != "clock" =>
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(name -> Output(regenLeafType(tpe)))
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})
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val enable = Output(Bool())
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@ -16,7 +16,7 @@ class DefaultF1Config extends Config(new Config((site, here, up) => {
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case DesiredHostFrequency => 75
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case SynthAsserts => true
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case midas.GenerateMultiCycleRamModels => true
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case SynthPrints => false
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case SynthPrints => true
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}) ++ new Config(new firesim.configs.WithEC2F1Artefacts ++ new WithDefaultMemModel ++ new midas.F1Config))
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class PointerChaserConfig extends Config((site, here, up) => {
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