[platform] Cleanup debug printfs in F1 Shim
This commit is contained in:
David Biancolin
parent
83e0c01792
commit
17927595b7
|
|
@ -30,8 +30,42 @@ class Nasti2AXI4IdentityModule(params: AXI4BundleParameters)(implicit p: Paramet
|
|||
io.nasti.b.bits.user := io.axi4.b.bits.user.getOrElse(DontCare)
|
||||
}
|
||||
|
||||
class Nasti2AXI4Monitor(params: AXI4BundleParameters)(implicit p: Parameters) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val axi4 = Output(new AXI4Bundle(params))
|
||||
val nasti = Input(new NastiIO()(p alterPartial { case NastiKey => NastiParameters(params) } ))
|
||||
})
|
||||
import chisel3.ExplicitCompileOptions.NotStrict
|
||||
io.axi4 := io.nasti
|
||||
}
|
||||
|
||||
/**
|
||||
* THe Nasti -> AXI4 implies here that all methods of this object accept
|
||||
* NastiIO as their primary argument. NB: the Nasti bundle may be mastered or be mastered
|
||||
* by the resulting AXI4.
|
||||
*
|
||||
*/
|
||||
object Nasti2AXI4 {
|
||||
def convertFromAXI4Sink(axi4Sink: AXI4Bundle)(implicit p: Parameters): NastiIO = {
|
||||
// Coerces a nastiIO bundle to all source-flow for use in a monitor or printf
|
||||
def toMonitor(nastiIO: NastiIO)(implicit p: Parameters): AXI4Bundle = {
|
||||
val axi4Params = AXI4BundleParameters(nastiIO.ar.bits.addr.getWidth,
|
||||
nastiIO.r.bits.data.getWidth,
|
||||
nastiIO.ar.bits.id .getWidth,
|
||||
nastiIO.ar.bits.user.getWidth)
|
||||
val conv = Module(new Nasti2AXI4Monitor(axi4Params))
|
||||
conv.io.nasti := nastiIO
|
||||
conv.io.axi4
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* THe AXI4 -> Nastplies here that all methods of this object accept
|
||||
* AXI4 as their primary argument.
|
||||
*
|
||||
*/
|
||||
object AXI42Nasti {
|
||||
// Returns an nasti bundle that drives the argument (a sink-flow AXI4 bundle).
|
||||
def fromSink(axi4Sink: AXI4Bundle)(implicit p: Parameters): NastiIO = {
|
||||
val conv = Module(new Nasti2AXI4IdentityModule(axi4Sink.params))
|
||||
axi4Sink <> conv.io.axi4
|
||||
conv.io.nasti
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule}
|
|||
import freechips.rocketchip.util.HeterogeneousBag
|
||||
|
||||
import midas.core.{DMANastiKey, HostMemNumChannels}
|
||||
import midas.widgets.{AXI4Printf}
|
||||
|
||||
case object AXIDebugPrint extends Field[Boolean]
|
||||
|
||||
|
|
@ -20,197 +21,17 @@ class F1ShimIO(implicit val p: Parameters) extends Bundle {
|
|||
class F1Shim(implicit p: Parameters) extends PlatformShim {
|
||||
val io = IO(new F1ShimIO)
|
||||
val top = Module(LazyModule(new midas.core.FPGATop).module)
|
||||
val io_slave = IO(HeterogeneousBag(top.mem.map(x => x.cloneType)))
|
||||
val headerConsts = top.headerConsts
|
||||
|
||||
val cyclecount = RegInit(0.U(64.W))
|
||||
cyclecount := cyclecount + 1.U
|
||||
|
||||
if (p(AXIDebugPrint)) {
|
||||
// print all transactions
|
||||
when (io.master.aw.fire()) {
|
||||
printf("[master,awfire,%x] addr %x, len %x, size %x, burst %x, lock %x, cache %x, prot %x, qos %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.master.aw.bits.addr,
|
||||
io.master.aw.bits.len,
|
||||
io.master.aw.bits.size,
|
||||
io.master.aw.bits.burst,
|
||||
io.master.aw.bits.lock,
|
||||
io.master.aw.bits.cache,
|
||||
io.master.aw.bits.prot,
|
||||
io.master.aw.bits.qos,
|
||||
io.master.aw.bits.id,
|
||||
io.master.aw.bits.user
|
||||
)
|
||||
}
|
||||
|
||||
when (io.master.w.fire()) {
|
||||
printf("[master,wfire,%x] data %x, last %x, id %x, strb %x, user %x\n",
|
||||
cyclecount,
|
||||
io.master.w.bits.data,
|
||||
io.master.w.bits.last,
|
||||
io.master.w.bits.id,
|
||||
io.master.w.bits.strb,
|
||||
io.master.w.bits.user
|
||||
)
|
||||
}
|
||||
|
||||
when (io.master.b.fire()) {
|
||||
printf("[master,bfire,%x] resp %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.master.b.bits.resp,
|
||||
io.master.b.bits.id,
|
||||
io.master.b.bits.user
|
||||
)
|
||||
}
|
||||
|
||||
when (io.master.ar.fire()) {
|
||||
printf("[master,arfire,%x] addr %x, len %x, size %x, burst %x, lock %x, cache %x, prot %x, qos %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.master.ar.bits.addr,
|
||||
io.master.ar.bits.len,
|
||||
io.master.ar.bits.size,
|
||||
io.master.ar.bits.burst,
|
||||
io.master.ar.bits.lock,
|
||||
io.master.ar.bits.cache,
|
||||
io.master.ar.bits.prot,
|
||||
io.master.ar.bits.qos,
|
||||
io.master.ar.bits.id,
|
||||
io.master.ar.bits.user
|
||||
)
|
||||
}
|
||||
|
||||
when (io.master.r.fire()) {
|
||||
printf("[master,rfire,%x] resp %x, data %x, last %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.master.r.bits.resp,
|
||||
io.master.r.bits.data,
|
||||
io.master.r.bits.last,
|
||||
io.master.r.bits.id,
|
||||
io.master.r.bits.user
|
||||
)
|
||||
}
|
||||
|
||||
when (io.dma.aw.fire()) {
|
||||
printf("[dma,awfire,%x] addr %x, len %x, size %x, burst %x, lock %x, cache %x, prot %x, qos %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.dma.aw.bits.addr,
|
||||
io.dma.aw.bits.len,
|
||||
io.dma.aw.bits.size,
|
||||
io.dma.aw.bits.burst,
|
||||
io.dma.aw.bits.lock,
|
||||
io.dma.aw.bits.cache,
|
||||
io.dma.aw.bits.prot,
|
||||
io.dma.aw.bits.qos,
|
||||
io.dma.aw.bits.id,
|
||||
io.dma.aw.bits.user)
|
||||
}
|
||||
|
||||
when (io.dma.w.fire()) {
|
||||
printf("[dma,wfire,%x] data %x, last %x, id %x, strb %x, user %x\n",
|
||||
cyclecount,
|
||||
io.dma.w.bits.data,
|
||||
io.dma.w.bits.last,
|
||||
io.dma.w.bits.strb,
|
||||
io.dma.w.bits.user)
|
||||
}
|
||||
|
||||
when (io.dma.b.fire()) {
|
||||
printf("[dma,bfire,%x] resp %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.dma.b.bits.resp,
|
||||
io.dma.b.bits.id,
|
||||
io.dma.b.bits.user)
|
||||
}
|
||||
|
||||
when (io.dma.ar.fire()) {
|
||||
printf("[dma,arfire,%x] addr %x, len %x, size %x, burst %x, lock %x, cache %x, prot %x, qos %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.dma.ar.bits.addr,
|
||||
io.dma.ar.bits.len,
|
||||
io.dma.ar.bits.size,
|
||||
io.dma.ar.bits.burst,
|
||||
io.dma.ar.bits.lock,
|
||||
io.dma.ar.bits.cache,
|
||||
io.dma.ar.bits.prot,
|
||||
io.dma.ar.bits.qos,
|
||||
io.dma.ar.bits.id)
|
||||
}
|
||||
|
||||
when (io.dma.r.fire()) {
|
||||
printf("[dma,rfire,%x] resp %x, data %x, last %x, id %x\n",
|
||||
cyclecount,
|
||||
io.dma.r.bits.resp,
|
||||
io.dma.r.bits.data,
|
||||
io.dma.r.bits.last,
|
||||
io.dma.r.bits.id)
|
||||
}
|
||||
|
||||
when (io_slave(0).aw.fire()) {
|
||||
printf("[slave,awfire,%x] addr %x, len %x, size %x, burst %x, lock %x, cache %x, prot %x, qos %x, id %x\n",
|
||||
cyclecount,
|
||||
|
||||
io_slave(0).aw.bits.addr,
|
||||
io_slave(0).aw.bits.len,
|
||||
io_slave(0).aw.bits.size,
|
||||
io_slave(0).aw.bits.burst,
|
||||
io_slave(0).aw.bits.lock,
|
||||
io_slave(0).aw.bits.cache,
|
||||
io_slave(0).aw.bits.prot,
|
||||
io_slave(0).aw.bits.qos,
|
||||
io_slave(0).aw.bits.id
|
||||
)
|
||||
AXI4Printf(io.master, "master")
|
||||
AXI4Printf(io.dma, "dma")
|
||||
io_slave.zipWithIndex foreach { case (io, idx) => AXI4Printf(io, s"slave_${idx}") }
|
||||
}
|
||||
|
||||
when (io_slave(0).w.fire()) {
|
||||
printf("[slave(0),wfire,%x] data %x, last %x, id %x, strb %x\n",
|
||||
cyclecount,
|
||||
|
||||
io_slave(0).w.bits.data,
|
||||
io_slave(0).w.bits.last,
|
||||
io_slave(0).w.bits.strb)
|
||||
}
|
||||
|
||||
when (io_slave(0).b.fire()) {
|
||||
printf("[slave(0),bfire,%x] resp %x, id %x\n",
|
||||
cyclecount,
|
||||
|
||||
io_slave(0).b.bits.resp,
|
||||
io_slave(0).b.bits.id
|
||||
)
|
||||
}
|
||||
|
||||
when (io_slave(0).ar.fire()) {
|
||||
printf("[slave(0),arfire,%x] addr %x, len %x, size %x, burst %x, lock %x, cache %x, prot %x, qos %x, id %x\n",
|
||||
cyclecount,
|
||||
|
||||
io_slave(0).ar.bits.addr,
|
||||
io_slave(0).ar.bits.len,
|
||||
io_slave(0).ar.bits.size,
|
||||
io_slave(0).ar.bits.burst,
|
||||
io_slave(0).ar.bits.lock,
|
||||
io_slave(0).ar.bits.cache,
|
||||
io_slave(0).ar.bits.prot,
|
||||
io_slave(0).ar.bits.qos,
|
||||
io_slave(0).ar.bits.id
|
||||
)
|
||||
}
|
||||
|
||||
when (io_slave(0).r.fire()) {
|
||||
printf("[slave(0),rfire,%x] resp %x, data %x, last %x, id %x\n",
|
||||
cyclecount,
|
||||
|
||||
io_slave(0).r.bits.resp,
|
||||
io_slave(0).r.bits.data,
|
||||
io_slave(0).r.bits.last,
|
||||
io_slave(0).r.bits.id
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
top.io.ctrl <> io.master
|
||||
top.io.dma <> io.dma
|
||||
val io_slave = IO(HeterogeneousBag(top.mem.map(x => x.cloneType)))
|
||||
io_slave.zip(top.mem).foreach({ case (io, bundle) => io <> bundle })
|
||||
|
||||
val (wCounterValue, wCounterWrap) = Counter(io.master.aw.fire(), 4097)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,78 @@
|
|||
/// See LICENSE for license details.
|
||||
|
||||
package midas.widgets
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import junctions._
|
||||
import freechips.rocketchip.amba.axi4.AXI4Bundle
|
||||
import freechips.rocketchip.config.{Parameters, Field}
|
||||
|
||||
object AXI4Printf {
|
||||
def apply(io: AXI4Bundle, name: String): Unit = {
|
||||
val cyclecount = RegInit(0.U(64.W))
|
||||
cyclecount := cyclecount + 1.U
|
||||
when (io.aw.fire()) {
|
||||
printf(s"[${name},awfire,%x] addr %x, len %x, size %x, burst %x, lock %x, cache %x, prot %x, qos %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.aw.bits.addr,
|
||||
io.aw.bits.len,
|
||||
io.aw.bits.size,
|
||||
io.aw.bits.burst,
|
||||
io.aw.bits.lock,
|
||||
io.aw.bits.cache,
|
||||
io.aw.bits.prot,
|
||||
io.aw.bits.qos,
|
||||
io.aw.bits.id,
|
||||
io.aw.bits.user.getOrElse(0.U)
|
||||
)
|
||||
}
|
||||
|
||||
when (io.w.fire()) {
|
||||
printf(s"[${name},wfire,%x] data %x, last %x, strb %x\n",
|
||||
cyclecount,
|
||||
io.w.bits.data,
|
||||
io.w.bits.last,
|
||||
io.w.bits.strb,
|
||||
)
|
||||
}
|
||||
|
||||
when (io.b.fire()) {
|
||||
printf(s"[${name},bfire,%x] resp %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.b.bits.resp,
|
||||
io.b.bits.id,
|
||||
io.b.bits.user.getOrElse(0.U)
|
||||
)
|
||||
}
|
||||
|
||||
when (io.ar.fire()) {
|
||||
printf(s"[${name},arfire,%x] addr %x, len %x, size %x, burst %x, lock %x, cache %x, prot %x, qos %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.ar.bits.addr,
|
||||
io.ar.bits.len,
|
||||
io.ar.bits.size,
|
||||
io.ar.bits.burst,
|
||||
io.ar.bits.lock,
|
||||
io.ar.bits.cache,
|
||||
io.ar.bits.prot,
|
||||
io.ar.bits.qos,
|
||||
io.ar.bits.id,
|
||||
io.ar.bits.user.getOrElse(0.U)
|
||||
)
|
||||
}
|
||||
|
||||
when (io.r.fire()) {
|
||||
printf(s"[${name},rfire,%x] resp %x, data %x, last %x, id %x, user %x\n",
|
||||
cyclecount,
|
||||
io.r.bits.resp,
|
||||
io.r.bits.data,
|
||||
io.r.bits.last,
|
||||
io.r.bits.id,
|
||||
io.r.bits.user.getOrElse(0.U)
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
def apply(io: NastiIO, name: String)(implicit p: Parameters): Unit = apply(Nasti2AXI4.toMonitor(io), name)
|
||||
}
|
||||
|
|
@ -94,7 +94,7 @@ class LoadMemWidget(val totalDRAMAllocated: BigInt)(implicit p: Parameters) exte
|
|||
val maxBurst = edge.slave.slaves.map(s => min(s.supportsRead.max, s.supportsWrite.max)).min / (edge.bundle.dataBits / 8)
|
||||
val io = IO(new LoadMemIO)
|
||||
// Gives us a bi-directional hook to a nasti interface so we don't have to port all the code below
|
||||
val memNasti = Nasti2AXI4.convertFromAXI4Sink(memAXI4)
|
||||
val memNasti = AXI42Nasti.fromSink(memAXI4)
|
||||
|
||||
// prefix h -> host memory we are writing to
|
||||
// prefix c -> control nasti interface who is the master of this unit
|
||||
|
|
|
|||
|
|
@ -14,51 +14,6 @@ import junctions.{NastiKey, NastiParameters}
|
|||
import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
|
||||
import midas.widgets.{PeekPokeBridge, RationalClockBridge}
|
||||
|
||||
object AXI4Printf {
|
||||
def apply(axi4: AXI4Bundle): Unit = {
|
||||
val tCycle = RegInit(0.U(32.W))
|
||||
tCycle.suggestName("tCycle")
|
||||
tCycle := tCycle + 1.U
|
||||
|
||||
when (axi4.ar.fire) {
|
||||
printf("TCYCLE: %d, AR addr: %x, id: %d, size: %d, len: %d\n",
|
||||
tCycle,
|
||||
axi4.ar.bits.addr,
|
||||
axi4.ar.bits.id,
|
||||
axi4.ar.bits.size,
|
||||
axi4.ar.bits.len)
|
||||
}
|
||||
|
||||
when (axi4.aw.fire) {
|
||||
printf("TCYCLE: %d, AW addr: %x, id: %d, size: %d, len: %d\n",
|
||||
tCycle,
|
||||
axi4.aw.bits.addr,
|
||||
axi4.aw.bits.id,
|
||||
axi4.aw.bits.size,
|
||||
axi4.aw.bits.len)
|
||||
}
|
||||
when (axi4.w.fire) {
|
||||
printf("TCYCLE: %d, W data: %x, last: %b\n",
|
||||
tCycle,
|
||||
axi4.w.bits.data,
|
||||
axi4.w.bits.last)
|
||||
}
|
||||
|
||||
when (axi4.r.fire) {
|
||||
printf("TCYCLE: %d, R data: %x, last: %b, id: %d\n",
|
||||
tCycle,
|
||||
axi4.r.bits.data,
|
||||
axi4.r.bits.last,
|
||||
axi4.r.bits.id)
|
||||
}
|
||||
when (axi4.b.fire) {
|
||||
printf("TCYCLE: %d, B id: %d\n", tCycle, axi4.r.bits.id)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
// TODO: Handle errors and reinstatiate the TLErrorEvaluator
|
||||
class AXI4FuzzerDUT(implicit p: Parameters) extends LazyModule with HasFuzzTarget {
|
||||
val fuzz = LazyModule(new TLFuzzer(p(NumTransactions), p(MaxFlight)))
|
||||
|
|
@ -102,7 +57,6 @@ class AXI4FuzzerDUT(implicit p: Parameters) extends LazyModule with HasFuzzTarge
|
|||
val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
|
||||
axi4.ar.bits.addr.getWidth,
|
||||
axi4.ar.bits.id.getWidth)
|
||||
AXI4Printf(axi4)
|
||||
val fasedInstance = FASEDBridge(clock, axi4, reset.toBool,
|
||||
CompleteConfig(p(firesim.configs.MemModelKey),
|
||||
nastiKey,
|
||||
|
|
|
|||
Loading…
Reference in New Issue