35e45c9b76
[asserts] Convert assert nodes to stop + print early
2022-01-25 20:46:37 +00:00
bdec8d667d
Catch new assertion nodes that would present to Synthesis and fail
2022-01-25 20:45:30 +00:00
9c778b6cd7
Re-add cloneType to more record types
2022-01-21 16:06:36 -08:00
1bf9ece693
Fix warnings and some errors
2022-01-21 14:20:45 -08:00
5f27114ade
Remove deprecated cloneTypes
2022-01-17 21:43:09 -08:00
fce4cab59d
Bump fix: Ensure added Print statements have names
2021-12-14 22:30:44 +00:00
b77f427faf
[midasexamples] Use RC generator to avoid depenency on chipyard
2021-12-14 22:30:35 +00:00
0cc4a17ed8
Merge pull request #864 from firesim/factor-out-peek-poke
...
Factor peek/poke out of simif_t
2021-12-14 13:31:29 -08:00
28bb6f2a9b
Correct multicycle hold-time constraint
2021-12-06 23:16:26 +00:00
7591ff12cf
Copy in FIRRTL testutils into midas
2021-12-01 23:56:58 +00:00
321a98f9f7
remove unused(deprecated) APIs. ( #892 )
...
(cherry picked from commit 06398cb49a78276599f2a54f877dd30fc967d205)
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-12-01 12:36:37 -08:00
889d49b046
fased: Use right NastiKey to calculate TLError address ( #881 )
2021-11-19 13:53:58 -08:00
3500497a16
[targetutils] Check annotators expect hardware types where appropriate ( #865 )
...
* [targetutils] Check annotators expect hardware types where appropriate
* Update annotations.scala
[ci skip]
2021-11-11 15:25:41 -08:00
6935b34285
More cleanly separate init/finish from host IF
2021-10-28 21:01:36 +00:00
60310c6b8a
Factor peek/poke out of simif_t
2021-10-28 16:14:52 +00:00
1f17b5fc83
Remove all zynq-related code. ( #863 )
2021-10-27 14:25:02 -04:00
a469544bee
Convert MMIO word addresses -> byte addresses ( #857 )
...
* Convert MMIO word addresses -> byte addresses
This makes address handling more uniform across the RTL and driver, leading to fewer points of confusion, and making it simpler to debug waveforms.
* Fix wide peeks and pokes
2021-10-26 16:46:25 -04:00
015dc8d784
patching widht-mismatch lints ( #860 )
...
(cherry picked from commit b344810d00b9c5ec7e105fdb0f3552ee0c733c7a)
Co-authored-by: rahulb10 <rahul.bodduna@gmail.com>
2021-10-22 13:03:23 -07:00
52198f6f16
[stage] Have runtime config generator use the checks phase
2021-10-15 18:06:37 -07:00
636f356c75
stage: Ban use of -o, -E. Introduce AddDerivedAnnotations Phase
2021-10-15 18:06:37 -07:00
c29acaf619
[stage] Add a checks phase + test
2021-10-15 18:06:37 -07:00
e4a77639b7
remove property ( #847 )
...
(cherry picked from commit 95adc9a8cae268b4c22252d81992c724fc8f8db9)
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-10-07 22:20:33 -07:00
1f015341c2
Emit multi-cycle clock constraints on target domains
2021-09-25 01:49:10 +00:00
d010640a79
Apply suggestions from code review
...
[ci skip]
Co-authored-by: Tim Snyder <timothy.snyder@sifive.com>
2021-09-15 16:35:50 -07:00
97d3ed8ad2
Apply suggestions from code review
...
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2021-09-15 22:28:11 +00:00
0a6fe70da4
fixup! Add mechanism for hierarchy-mutation robust XDC generation
2021-09-15 22:28:11 +00:00
977c467167
Add tests for XDC emission
2021-09-15 22:28:11 +00:00
2aa454b7a5
Add mechanism for hierarchy-mutation robust XDC generation
2021-09-15 22:28:11 +00:00
7f773ea991
Update AnnotationWiringTransform to support missing sinks
2021-09-09 19:44:14 +00:00
9598f1efe9
Merge pull request #816 from firesim/selective-dram-utilization
...
Selective DRAM Channel Instantiation
2021-08-27 18:09:24 -04:00
9e27ccd2b6
Correct a typo in simif_f1.cc ( #821 )
...
(cherry picked from commit 3dd82c248ca30d33f69f52ddca297fa451419317)
Co-authored-by: Felix Yan <felixonmars@archlinux.org>
2021-08-11 16:03:46 -04:00
1130d03656
Selectively instantiate DRAM controllers based on required memory
2021-08-10 15:26:46 +00:00
4914a66905
Implement globalResetCondition support
2021-08-06 20:20:54 +00:00
c4e3b077d0
[passes] Add an annotation-parameterized WiringTransform wrapper
2021-08-06 20:20:54 +00:00
2f1eb36205
[targetutils] Add a utility to block promote passthrough opts
2021-08-06 20:20:54 +00:00
61ad72abc4
[targetutils] Add Chisel-side API for labelling the reset condition
2021-08-06 20:20:54 +00:00
fa72045afc
Rename Assert.scala -> AssertBridge.scala
2021-08-06 20:20:54 +00:00
1a7f0265c0
Rename AssertPass -> AssertionSynthesis
2021-08-06 20:20:54 +00:00
548270ae5a
Merge pull request #782 from firesim/reset-bridge
...
Introduce a ResetPulseBridge to Remove An Early Deadlock Condition
2021-08-06 16:16:45 -04:00
76654ce6c2
Merge pull request #802 from firesim/file-emission
...
Use a Standard File Emission Strategy
2021-08-06 12:23:23 -04:00
6258aea8ca
[bridges] Add a result pulse bridge to replace peek/poke
2021-08-06 16:00:54 +00:00
b9d92ceaa2
Update unitests to use new makefrag variables
2021-07-29 22:40:49 +00:00
c93b2eb728
Strip out calls in the MIDAS makefile
2021-07-29 22:40:49 +00:00
2e30100d35
Use new file emission trait + makefile naming cleanup
2021-07-29 22:40:49 +00:00
fa8b1a98f8
Add a PhaseManager to do subcircuit elaborations
2021-07-29 22:32:49 +00:00
5c4f3eca1e
[stage] Stop serialization of GG option annotations
2021-07-29 22:32:49 +00:00
d057bf0423
[stage] Add utilities to harmonize file emission
2021-07-29 22:32:49 +00:00
dea18b98d7
Update sim/midas/src/main/scala/midas/widgets/Bridge.scala
2021-07-14 15:48:15 -07:00
2a44e0fdf8
Add some initial scalatests for ChannelizedHostPortIO
2021-07-14 21:34:05 +00:00
fa8eae08f2
Improve Bridge Host IFs
2021-07-14 21:34:05 +00:00
David Biancolin