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Fix TracerV test

This commit is contained in:
David Biancolin 2019-06-21 17:18:33 -07:00
parent e9521e0344
commit 503d2135c5
2 changed files with 7 additions and 3 deletions
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2
sim/midas

@ -1 +1 @@
Subproject commit 8644a571dc5919cd6a1962ef6f100050fa4ac42a
Subproject commit c52d7e740fe448c9da5fe3dc1223125b36571ceb

8
sim/src/test/scala/firesim/ScalaTestSuite.scala
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@ -111,8 +111,12 @@ abstract class FireSimTestSuite(
}
val resetLength = 50
val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}"))
val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength + 1)
assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length")
val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength)
// We allow one extra token in the synthesized log since it may slip
// ahead of the rest of the model by a single cycle
assert(((verilatedOutput.size + 1) == synthPrintOutput.size)||
verilatedOutput.size == synthPrintOutput.size,
"Outputs differ in length")
assert(verilatedOutput.nonEmpty)
for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
assert(vPrint == sPrint)