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[print] Use new clock info class

This commit is contained in:
David Biancolin 2020-03-18 10:56:03 -07:00
parent 68d68db089
commit 69c9ad11ad
3 changed files with 7 additions and 12 deletions
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9
sim/midas/src/main/cc/bridges/synthesized_prints.cc
View File

@ -30,9 +30,7 @@ synthesized_prints_t::synthesized_prints_t(
argument_counts(argument_counts),
argument_widths(argument_widths),
dma_address(dma_address),
clock_domain_name(clock_domain_name),
clock_multiplier(clock_multiplier),
clock_divisor(clock_divisor),
clock_info(clock_domain_name, clock_multiplier, clock_divisor),
printno(printno) {
assert((token_bytes & (token_bytes - 1)) == 0);
assert(print_count > 0);
@ -68,11 +66,11 @@ synthesized_prints_t::synthesized_prints_t(
}
if (arg.find(printstart_arg) == 0) {
char *str = const_cast<char*>(arg.c_str()) + printstart_arg.length();
this->start_cycle = (atol(str) * clock_multiplier) / clock_divisor;
this->start_cycle = this->clock_info.to_local_cycles(atol(str));
}
if (arg.find(printend_arg) == 0) {
char *str = const_cast<char*>(arg.c_str()) + printend_arg.length();
this->end_cycle = (atol(str) * clock_multiplier) / clock_divisor;
this->end_cycle = this->clock_info.to_local_cycles(atol(str));
}
if (arg.find(binary_arg) == 0) {
human_readable = false;
@ -90,6 +88,7 @@ synthesized_prints_t::synthesized_prints_t(
}
this->printstream = &(this->printfile);
this->clock_info.emit_file_header(*(this->printstream));
widths.resize(print_count);
// Used to reconstruct the relative position of arguments in the flattened argument_widths array

5
sim/midas/src/main/cc/bridges/synthesized_prints.h
View File

@ -9,6 +9,7 @@
#include <gmp.h>
#include "bridge_driver.h"
#include "clock_info.h"
// Bridge Driver Instantiation Template
#define INSTANTIATE_PRINTF(FUNC,IDX) \
@ -76,9 +77,7 @@ class synthesized_prints_t: public bridge_driver_t
const unsigned int* argument_counts;
const unsigned int* argument_widths;
const unsigned int dma_address;
const char* const clock_domain_name;
const unsigned int clock_multiplier;
const unsigned int clock_divisor;
ClockInfo clock_info;
const int printno;
// DMA batching parameters

5
sim/midas/src/main/scala/midas/widgets/Print.scala
View File

@ -173,7 +173,6 @@ class PrintBridgeModule(printPorts: Seq[(firrtl.ir.Port, String)])(implicit p: P
val argumentWidths = printPort.ports.flatMap(_._2.argumentWidths).map(UInt32(_))
val argumentOffsets = printPort.ports.map(_._2.argumentOffsets.map(UInt32(_)))
val formatStrings = printPort.ports.map(_._2.formatString).map(CStrLit)
val RationalClock(domainName, mul, div) = clockDomainInfo
override def genHeader(base: BigInt, sb: StringBuilder) {
import CppGenerationUtils._
@ -187,9 +186,7 @@ class PrintBridgeModule(printPorts: Seq[(firrtl.ir.Port, String)])(implicit p: P
sb.append(genArray(s"${headerWidgetName}_format_strings", formatStrings))
sb.append(genArray(s"${headerWidgetName}_argument_counts", argumentCounts))
sb.append(genArray(s"${headerWidgetName}_argument_widths", argumentWidths))
sb.append(genStatic(s"${headerWidgetName}_clock_domain_name", CStrLit(domainName)))
sb.append(genConstStatic(s"${headerWidgetName}_clock_multiplier", UInt32(mul)))
sb.append(genConstStatic(s"${headerWidgetName}_clock_divisor", UInt32(div)))
emitClockDomainInfo(headerWidgetName, sb)
}
genCRFile()
}