[print] Update plusargs to synthesized printf driver

docs/Advanced-Usage/Debugging/printf-synthesis.rst

@@ -53,11 +53,16 @@ Runtime Arguments
     Specifies the target cycle at which to stop pulling the synthesized print
     trace from the simulator.
 
-**+print-human-readable**
-    By default, a captured printf trace will be written to file as a raw,
-    unformatted binary, as properly formatting the printf further slows the
-    simulator.  Setting this will properly format the print data before writing
-    it to file.
+**+print-binary**
+    By default, a captured printf trace will be written to file formatted
+    as it would be emitted by a software RTL simulator. Setting this dumps the
+    raw binary coming off the FPGA instead, improving simulation rate.
+
+**+print-no-cycle-prefix**
+    (Formatted output only) This removes the cycle prefix from each printf to
+    save bandwidth in cases where the printf already includes a cycle field. In
+    binary-output mode, since the target cycle is implicit in the token stream,
+    this flag has no effect.
 
 Related Publications
 --------------------

sim/midas

@@ -1 +1 @@
-Subproject commit 166bb8c5fcd98589ee2809174a6689fc8ef7c2a7
+Subproject commit 8228bd4fce19ff31f69291332e66b9856928f7c6

sim/src/test/scala/midasexamples/TutorialSuite.scala

@@ -128,10 +128,10 @@ class RiscF1Test extends TutorialSuite("Risc")
 class RiscSRAMF1Test extends TutorialSuite("RiscSRAM")
 class AssertModuleF1Test extends TutorialSuite("AssertModule")
 class PrintfModuleF1Test extends TutorialSuite("PrintfModule",
-  simulationArgs = Seq("+print-human-readable", "+print-file=synthprinttest.out")) {
+  simulationArgs = Seq("+print-file=synthprinttest.out")) {
   diffSynthesizedPrints("synthprinttest.out")
 }
 class NarrowPrintfModuleF1Test extends TutorialSuite("NarrowPrintfModule",
-  simulationArgs = Seq("+print-human-readable", "+print-file=synthprinttest.out")) {
+  simulationArgs = Seq("+print-file=synthprinttest.out")) {
   diffSynthesizedPrints("synthprinttest.out")
 }