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[gg] Move Compiler.scala -> passes/Compilers.scala

This commit is contained in:
David Biancolin 2019-11-06 10:30:20 -08:00
parent a090464263
commit 9d1b4f81a0
3 changed files with 12 additions and 18 deletions
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7
sim/midas/src/main/scala/midas/Config.scala
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@ -11,6 +11,8 @@ import junctions.{NastiKey, NastiParameters}
import freechips.rocketchip.config.{Parameters, Config, Field}
import freechips.rocketchip.unittest.UnitTests
import java.io.{File}
// Provides a function to elaborate the top-level platform shim
case object Platform extends Field[(Parameters) => PlatformShim]
// Switches to synthesize prints and assertions
@ -22,7 +24,7 @@ case object EnableSnapshot extends Field[Boolean]
case object HasDMAChannel extends Field[Boolean]
case object KeepSamplesInMem extends Field[Boolean]
// MIDAS 2.0 Switches
// Enables multi-cycle RAM model generation (as demonstrated in the ICCAD2019 paper)
case object GenerateMultiCycleRamModels extends Field[Boolean](false)
// User provided transforms to run before Golden Gate transformations
// These are constructor functions accept a Parameters instance and produce a
@ -31,6 +33,9 @@ case object TargetTransforms extends Field[Seq[(Parameters) => Seq[firrtl.Transf
// User provided transforms to run after Golden Gate transformations
case object HostTransforms extends Field[Seq[(Parameters) => Seq[firrtl.Transform]]](Seq())
// Directory into which output files are dumped. Set by -td when invoking the Stage
case object OutputDir extends Field[File]
class SimConfig extends Config((site, here, up) => {
case TraceMaxLen => 1024
case SRAMChainNum => 1

22
sim/midas/src/main/scala/midas/Compiler.scala → sim/midas/src/main/scala/midas/passes/Compilers.scala
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@ -1,25 +1,13 @@
// See LICENSE for license details.
package midas
package midas.passes
import passes.Utils.writeEmittedCircuit
import chisel3.{Data, Bundle, Record, Clock, Bool}
import chisel3.internal.firrtl.Port
import firrtl.ir.Circuit
import firrtl.{Transform, CircuitState}
import firrtl.annotations.Annotation
import firrtl.CompilerUtils.getLoweringTransforms
import firrtl.passes.memlib._
import freechips.rocketchip.config.{Parameters, Field}
import java.io.{File, FileWriter, Writer}
import firrtl.passes.memlib.InferReadWrite
import logger._
// Directory into which output files are dumped. Set by dir argument
case object OutputDir extends Field[File]
// Compiler for Midas Transforms
private class MidasCompiler extends firrtl.Compiler {
private [midas] class MidasCompiler extends firrtl.Compiler {
def emitter = new firrtl.LowFirrtlEmitter
def transforms =
getLoweringTransforms(firrtl.ChirrtlForm, firrtl.MidForm) ++
@ -30,7 +18,7 @@ private class MidasCompiler extends firrtl.Compiler {
// These next two compilers split LFO from the rest of the lowering
// compilers to schedule around the presence of internal & non-standard WIR
// nodes (Dshlw) present after LFO, which custom transforms can't handle
private class HostTransformCompiler extends firrtl.Compiler {
private [midas] class HostTransformCompiler extends firrtl.Compiler {
def emitter = new firrtl.LowFirrtlEmitter
def transforms =
Seq(new firrtl.IRToWorkingIR,
@ -40,7 +28,7 @@ private class HostTransformCompiler extends firrtl.Compiler {
}
// Custom transforms have been scheduled -> do the final lowering
private class LastStageVerilogCompiler extends firrtl.Compiler {
private [midas] class LastStageVerilogCompiler extends firrtl.Compiler {
def emitter = new firrtl.VerilogEmitter
def transforms = Seq(new firrtl.LowFirrtlOptimization,
new firrtl.transforms.RemoveReset)

1
sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala
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@ -3,6 +3,7 @@
package midas.stage
import midas._
import midas.passes.{MidasCompiler, HostTransformCompiler, LastStageVerilogCompiler}
import firrtl.ir.Circuit
import firrtl.{Transform, CircuitState, AnnotationSeq}