The finest bugfix in my time at Berkeley

2019-11-22 15:47:21 -08:00 · 2019-11-22 15:47:21 -08:00 · cd559aa5d8
parent 619192e3f9
commit cd559aa5d8
1 changed files with 1 additions and 1 deletions
--- a/sim/midas/src/main/verilog/BUFGCE.v
+++ b/sim/midas/src/main/verilog/BUFGCE.v
@ -7,7 +7,7 @@ module BUFGCE(
   always @(posedge I)
     enable_latch <= CE;
 `ifdef VERILATOR
-   // Verilator doesn't like procedural clock gates
+   // Note: Verilator doesn't like procedural clock gates
   // They cause combinational loop errors and UNOPT_FLAT
   assign O = (I & enable_latch);
 `else