[print] Add a midasexample that packs narrow printf tokens

sim/midas

@@ -1 +1 @@
-Subproject commit efb32bfdc18f4d606a1f1a56dca04eee57edcbaf
+Subproject commit 86dcbfe8f2e1e664b2876d413c92b7a7bda8dde4

sim/src/main/cc/midasexamples/Driver.cc

@@ -29,6 +29,8 @@
 #include "AssertModule.h"
 #elif defined DESIGNNAME_PrintfModule
 #include "PrintfModule.h"
+#elif defined DESIGNNAME_NarrowPrintfModule
+#include "NarrowPrintfModule.h"
 #endif
 
 class dut_emul_t:

sim/src/main/cc/midasexamples/NarrowPrintfModule.h

@@ -0,0 +1,15 @@
+//See LICENSE for license details.
+
+#include "PrintfModule.h"
+class NarrowPrintfModule_t: public print_module_t, virtual simif_t
+{
+public:
+    NarrowPrintfModule_t(int argc, char** argv): print_module_t(argc, argv) {};
+    virtual void run() {
+        print_endpoint->init();
+        poke(reset, 1);
+        step(1);
+        poke(reset, 0);
+        run_and_collect_prints(256);
+    };
+};

sim/src/main/cc/midasexamples/PrintfModule.h

@@ -5,25 +5,41 @@
 #include "simif.h"
 #include "endpoints/synthesized_prints.h"
 
-class PrintfModule_t: virtual simif_t
+class print_module_t: virtual simif_t
+{
+    public:
+        std::unique_ptr<synthesized_prints_t> print_endpoint;
+        print_module_t(int argc, char** argv) {
+            PRINTWIDGET_0_substruct_create;
+            std::vector<std::string> args(argv + 1, argv + argc);
+            print_endpoint = std::unique_ptr<synthesized_prints_t>(new synthesized_prints_t(this,
+                args,
+                PRINTWIDGET_0_substruct,
+                PRINTWIDGET_0_print_count,
+                PRINTWIDGET_0_token_bytes,
+                PRINTWIDGET_0_print_offsets,
+                PRINTWIDGET_0_format_strings,
+                PRINTWIDGET_0_argument_counts,
+                PRINTWIDGET_0_argument_widths,
+                PRINTWIDGET_0_DMA_ADDR));
+        };
+        void run_and_collect_prints(int cycles) {
+            step(cycles, false);
+            while (!done()) {
+                print_endpoint->tick();
+            }
+            // Add a couple extra flushes to capture tokens that are collected after done is asserted.
+            print_endpoint->flush();
+            print_endpoint->flush();
+            print_endpoint->finish();
+        };
+};
+
+#ifdef DESIGNNAME_PrintfModule
+class PrintfModule_t: public print_module_t, virtual simif_t
 {
 public:
-    std::unique_ptr<synthesized_prints_t> print_endpoint;
-    PrintfModule_t(int argc, char** argv) {
-        PRINTWIDGET_0_substruct_create;
-        std::vector<std::string> args(argv + 1, argv + argc);
-        print_endpoint = std::unique_ptr<synthesized_prints_t>(new synthesized_prints_t(this,
-            args,
-            PRINTWIDGET_0_substruct,
-            PRINTWIDGET_0_print_count,
-            PRINTWIDGET_0_token_bytes,
-            PRINTWIDGET_0_print_offsets,
-            PRINTWIDGET_0_format_strings,
-            PRINTWIDGET_0_argument_counts,
-            PRINTWIDGET_0_argument_widths,
-            PRINTWIDGET_0_DMA_ADDR));
-    };
-
+    PrintfModule_t(int argc, char** argv): print_module_t(argc, argv) {};
     virtual void run() {
         print_endpoint->init();
         poke(reset, 1);
@@ -34,13 +50,7 @@ public:
         step(1);
         poke(a, 1);
         poke(b, 1);
-        step(128, false);
-        while (!done()) {
-            print_endpoint->tick();
-        }
-        // Add a couple extra flushes to capture tokens that are collected after done is asserted.
-        print_endpoint->flush();
-        print_endpoint->flush();
-        print_endpoint->finish();
+        run_and_collect_prints(256);
     };
 };
+#endif //DESIGNNAME_PrintfModule

sim/src/main/scala/midasexamples/PrintfModule.scala

@@ -3,6 +3,7 @@
 package firesim.midasexamples
 
 import chisel3._
+import chisel3.util.LFSR16
 import chisel3.experimental.MultiIOModule
 
 import midas.targetutils.SynthesizePrintf
@@ -34,5 +35,16 @@ class PrintfModuleChild extends MultiIOModule {
 
   val lfsr = chisel3.util.LFSR16(c)
   printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d LFSR: %x\n", cycle, lfsr))
+
+  //when (lsfr(0)) {
+  //  printf(SynthesizePrintf(p"SYNTHESIZED_PRINT CYCLE: ${cycle} LFSR is odd"))
+  //}
 }
 
+class NarrowPrintfModule extends MultiIOModule {
+  val cycle = RegInit(0.U(12.W))
+  cycle := cycle + 1.U
+  when(LFSR16()(0) & LFSR16()(0)) {
+    printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d\n", cycle))
+  }
+}

sim/src/test/scala/midasexamples/TutorialSuite.scala

@@ -115,3 +115,7 @@ class PrintfModuleF1Test extends TutorialSuite("PrintfModule", midas.F1,
   simulationArgs = Seq("+print-human-readable", "+printfile=synthprinttest.out")) {
   diffSynthesizedPrints("synthprinttest.out")
 }
+class NarrowPrintfModuleF1Test extends TutorialSuite("NarrowPrintfModule", midas.F1,
+  simulationArgs = Seq("+print-human-readable", "+printfile=synthprinttest.out")) {
+  diffSynthesizedPrints("synthprinttest.out")
+}