88e77d07f9
Merge remote-tracking branch 'origin/dev' into multiclock
2020-03-18 09:23:05 -07:00
53c8c9b693
Merge remote-tracking branch 'origin/dev' into fromajosim
2020-03-17 20:52:28 -07:00
def75eb18e
bugfix for 1 stream
2020-03-17 13:06:48 -07:00
fff18549bc
[print] Clean up some comments
2020-03-17 10:16:10 -07:00
55a45fc9f9
update makefiles to properly build driver | properly invoke simulator
2020-03-15 02:23:19 +00:00
afef8c13f5
[midas] add makefrag changes | add firesim_top.cc instantiation
2020-03-13 10:59:59 -07:00
6edc8a20dc
[printf] Use clock-domain info in print bridge & driver
2020-03-12 22:02:42 -07:00
0f3405cc3a
[Bridges] Provide target clock info through host Parameters
2020-03-12 22:01:08 -07:00
e13a236af0
[ClockBridge] Update API to accept RationalClock case classes
2020-03-12 21:58:44 -07:00
5cac9aaa75
[trigger] Mask events with reset if available
2020-03-12 09:42:29 -07:00
320f6360f1
[gg] Implement multi-clock compatible wiring
2020-03-11 15:33:07 -07:00
ab9b0c22e5
[rtlutils] Add a utility for generating reset-less registers
2020-03-11 15:33:07 -07:00
d0613c8d07
[fame] Add Neq to RTLUtils
2020-03-11 03:57:41 +00:00
2214c7bbc4
[midasexamples] Add a TriggerWiringModule integration test
2020-03-11 03:56:23 +00:00
7aae84d40f
[targetutils] Add Chisel API for triggering
2020-03-11 03:56:23 +00:00
6a55e6e931
[gg] Delete obselete ChannelizeTargetIO pass
2020-03-11 03:56:23 +00:00
42f6373009
[printf] Provide default printf filenames that don't collide
2020-03-11 03:56:23 +00:00
9f9705762a
[make] remove un-needed VCS flag
2020-03-09 17:50:32 -07:00
370230cf78
[make] re-add space for VCS
2020-03-09 16:07:51 -07:00
771f5532d8
Merge remote-tracking branch 'origin/dev' into firesim-blackbox-integration-cleanup
2020-03-07 21:45:38 +00:00
3271801d70
[make] move target specific flags to firesim makefrag
2020-03-06 22:23:09 +00:00
13bf4c1482
Remove unused CDC code
2020-03-05 20:43:35 -08:00
218a9f22c3
[AutoCounter] Include only common regnames in generated struct
2020-03-05 13:28:50 -08:00
fb458fe45f
[AutoCounter] Simplify the initialization process
...
It had weird behavior under multiclock
2020-03-05 13:10:54 -08:00
6ee1c04ea8
Remove an errant printf
2020-03-05 11:29:59 -08:00
1e938c62cc
[Bridge] Allow for registers to be excluded from struct
2020-03-05 11:29:27 -08:00
644fde8a67
[AutoCounter] DontTouch all signals
2020-03-05 11:28:02 -08:00
23b87ae9f8
[bridges] Disambiguate between printf bridge drivers
2020-03-03 17:09:39 -08:00
23b80238aa
dramsim stuff moved to chipyard/testchipip
2020-03-02 20:55:17 -08:00
32eb41f289
[WIP] Albert revert me! Disable FAME5 transform
2020-03-01 23:00:02 -08:00
00e167e363
[targetutils] Provide assert failure message for RTRenamer.exact
2020-03-01 22:57:25 -08:00
ccfbf5a3be
[gg] Overhaul AutoCounter for Multiclock support
...
In order to reuse BridgeTopWiring, i dropped the old the scheme of
instantiating the bridges as modules. As part of these changes I made
some other modifications / optimizations.
- AutoCounter Annotations now include a reset and clock ReferenceTarget
- PerfCounter apply uses the implicit clock and reset if available
- The bridge-based implementation no longer generates counters in the
target
- The Bool representing the event is wired to the bridge; and the
counter is instantiated there
- Saves on token queueing; 64 bit registers were already present in
the Bridge
- Bridge resource optimizations
- Smaller counter-sample queue (more queueing shouldn't doesn't improve
simulation performance under a fixed sample frequency).
- Fewer MMIO registers; simpler dequeue handshake logic saves a MMIO
transaction
2020-03-01 22:46:10 -08:00
4ef36824c0
[passes] Port printf synthesis to BridgeTopWiring
2020-03-01 13:44:40 -08:00
0b1ed5a691
[passes] BridgeTopWiring fixes
2020-03-01 13:42:47 -08:00
5a54dcf36c
[make] fix condition in ariane switch
2020-02-28 19:14:28 -08:00
5648fc0254
[verilator] bump to 4.028
2020-02-28 17:42:57 -08:00
8393a2370b
[make] cleanly swap between ariane and other flags
2020-02-28 16:56:36 -08:00
ee884b731e
[misc] cleanup makefiles | remove extra build recipe | revert docs on TracerV
2020-02-28 10:59:23 -08:00
8ed0c33100
[tests] Add a smoke test for BridgeTopWiring
2020-02-27 14:27:41 -08:00
b919213258
[passes] Add a BridgeTopWiring; tracks an associated clock
2020-02-27 14:26:17 -08:00
f00d681aa9
[make] add verilog generation to vcs/verilator dependency list | update vcs/verilator flags | extra sed'ing on verilog out
2020-02-25 16:26:55 -08:00
1d44793591
Merge remote-tracking branch 'origin/dev' into multiclock
...
Known issues:
- Clock analysis pass under printf synthesis has different behavior
- Async Reset seems to break FAME5 transform
- Autocounter nees to be ported
2020-02-13 12:16:33 -08:00
bf725a743f
[gg] Add a comment about CB counter widths
2020-02-12 18:28:35 -08:00
11074e435a
[gg] Move cycle counters to clock Bridge. Update FMR
2020-02-12 18:06:28 -08:00
a6accd5b5e
Update sim/midas/src/main/verilog/BUFGCE.v
...
Co-Authored-By: Albert Magyar <albert.magyar@gmail.com>
2020-02-11 23:00:36 -05:00
dd5dead368
[gg] Fix ram optimizations under clock-gating F1 xform
2020-02-11 18:05:07 -08:00
cd559aa5d8
The finest bugfix in my time at Berkeley
2020-02-07 01:45:34 +00:00
619192e3f9
Only use Verilator-friendly clock gate in Verilator sim
2020-02-07 01:45:34 +00:00
874e775507
Explicitly keep target clock gated while under reset
2020-02-07 01:45:34 +00:00
09af1a6d5a
Remove simReset
...
This was mostly unused and confusing. We're going to rely on reprogramming
for the foreseeable future as a means to deterministically reset the
simulator
2020-02-07 01:45:34 +00:00
6ae4f052eb
[synthPrintf] Use topWiringPrefix to prevent name collisions
2020-01-30 20:09:27 +00:00
82e05f05f6
Merge pull request #475 from firesim/parallel-verilator-compilation
...
[makefrag] Parallelize verilator-based ML-simulator compilation
2020-01-26 23:29:13 -08:00
c1b61cf1b4
[makefrag] Parallelize verilator-based ML-simulator compilation
2020-01-25 00:41:52 +00:00
3e4aab98e0
[docs] Add a UARTBridge Walkthrough
2020-01-22 12:48:05 -08:00
ef734c235f
Enable MuxingMultiThreader by default
2020-01-12 15:22:01 -08:00
8ce7935b39
Use small rocketchip ShiftQueues in channels
2020-01-12 15:21:26 -08:00
119d473964
Fix FAME5Info; fix write enables in MuxingMultiThreader
2020-01-12 15:20:51 -08:00
451956ef35
Add MuxedMultiThreader that produces mux-based microarchitecture
2020-01-12 02:55:55 -08:00
12a28d1c21
Fix handling of sync-read mems in FAME5 transform
2020-01-10 03:18:30 -08:00
522646cfb9
Merge branch 'multiclock' of github.com:firesim/firesim into multiclock
2020-01-09 02:00:12 -08:00
c9cc460979
WIP on FAME5, works for TwoAdder design
2020-01-09 02:00:04 -08:00
1b2824d6a8
[gg] Handle unconnected clock ports in FindClockSources
2020-01-08 12:01:55 -08:00
bfda4e71ba
[gg] Remove unneeded default annotations in FAMEDefaults
2019-12-19 17:24:19 -08:00
6cfdc30aee
[gg] Make FindClockSources a Transform; multiclock print synthesis
2019-12-17 23:32:44 -08:00
1cc01360b9
[autocounter] Workaround the host port problem
2019-12-17 15:33:38 -08:00
5f5c33f641
chisel bump modifications
2019-12-17 01:38:02 +00:00
1cde84538a
Allow multiple single-clock models to compose with a multi-clock hub model
2019-12-16 17:32:01 -08:00
1afabf56e8
Rename host clock from clock to hostClock
2019-12-16 17:28:19 -08:00
6c6c209589
[gg] Fix assert pass under no assertions
2019-12-16 15:36:31 -08:00
200b0e81c8
[manager] Do not copy over an asserts file
2019-12-16 11:30:49 -08:00
ebf082502c
[gg] Bring up multiclock assertion synthesis
2019-12-16 11:30:31 -08:00
a400d1ccff
Merge remote-tracking branch 'origin/dev' into triggers-counters-integration-clean
2019-12-16 11:23:46 -08:00
9621a15a00
[gg] Add a temporary utility to find clock sources
2019-12-10 16:31:53 -08:00
f28c1b1ba0
Merge in dev; bump chipyard; fix FSimAsTop
2019-12-10 22:48:11 +00:00
40b07d974f
address PR review comments from Albert
2019-12-10 00:37:25 -08:00
0ee151cf3e
Fix all projects for chisel 3.2.0
2019-12-09 08:47:42 -08:00
7ef7fe369f
move autocounter to midas, and address other PR comments
2019-12-06 23:13:33 -08:00
f7c3a97901
Fixes for chisel 3.2.0
2019-12-06 15:51:20 -08:00
dcabed76ae
AutoCounter transform and bridge for automatic perf counters
2019-12-02 22:14:24 -08:00
f1c21620fa
More info in assertion message
2019-12-02 22:10:38 -08:00
ff54c0f606
generate AddressMap for all widgets
2019-12-02 22:09:48 -08:00
538debe35b
Add TracerV trigger
2019-12-02 22:07:48 -08:00
74cd34baaf
[gg] Make SimulationMapping robust against target name collisions
2019-11-25 18:12:52 -08:00
2643c32d53
[gg] Bring up multiclock assertion synthesis; reenable AS in examples
2019-11-23 20:13:50 -08:00
1aaca790d1
The finest bugfix in my time at Berkeley
2019-11-22 15:47:21 -08:00
d22b57b770
Only use Verilator-friendly clock gate in Verilator sim
2019-11-20 15:02:35 -08:00
5b086b2ec4
[gg] Properly emit reverse decoupled channel annotations
2019-11-20 00:26:26 -08:00
26e326698b
[gg] Print out channels that are missing a clock in FAME1 xform
2019-11-20 00:25:43 -08:00
c2c436147c
[gg] Check that a single clock bridge instance is extracted
2019-11-19 23:55:57 -08:00
040610098d
[gg] Magyar-ify EnsureNoTargetIO
2019-11-19 23:34:47 -08:00
8aeed3484a
[gg] Also check for clock ports in EnsureNoTargetIO.scala
2019-11-19 22:58:32 -08:00
a9b0899cf1
[midasexamples] Bring up a simple test of multiclock
2019-11-18 11:28:32 -08:00
0ffbb5d149
Add raw module multithreader
2019-11-15 19:21:18 -08:00
61e7ee0481
[GG] Instantiate clock token generator; pipe clean sim wrapper
2019-11-14 23:03:59 -08:00
b1d99e7dd7
[GG] Make ClockBridgeAnnotation serializable
2019-11-14 22:43:47 -08:00
3937721552
[GG] Fix SimWrapper/Bridge related issues
2019-11-14 22:00:29 -08:00
562e162a8d
Delete DontTouch annos when transforming FAME models
2019-11-14 21:52:08 -08:00
83ab93c7d9
Makes it to SimWrapper generator
2019-11-14 11:05:30 -08:00
dbbe9d657c
Add logic to deal with clock channel connections
2019-11-13 14:27:21 -08:00
d95c3d2e83
More work on propagating channel clocks
2019-11-11 18:28:24 -08:00
9d1b4f81a0
[gg] Move Compiler.scala -> passes/Compilers.scala
2019-11-11 15:29:21 -08:00
a090464263
[gg] Remove defunct AddedTargetIOAnnotation; use bridges
2019-11-11 15:29:21 -08:00
ff905338d2
[gg] Stop passing around targetIO
2019-11-11 15:29:20 -08:00
051e5bb91d
[gg] Remove legacy Compiler object; use phase only
2019-11-11 15:29:20 -08:00
b07dbb7342
[gg] Remove platform mapping; change platform selection
2019-11-11 15:29:20 -08:00
854096f1f3
WIP on multiclock FAME transform
2019-11-10 21:14:52 -08:00
e151aa56b1
Make clock gating unconditional for now
2019-11-10 13:34:16 -08:00
4b69ba1390
Move patient SSM transformers to separate file
2019-11-10 13:32:26 -08:00
266dd7ac23
[gg] Rewrite irrevocable assertions in terms of leaf values
2019-11-05 14:23:34 -08:00
099e9db408
[gg] Put token irrevocability assertions on a switch
2019-11-04 16:10:48 -08:00
2fd68cfd80
Update token irrevocability assertion generation
2019-11-04 10:57:20 -08:00
014711691b
[WIP] Emit ClockChannel annotations using FCCA for now
2019-11-01 16:51:55 -07:00
dffab9fb13
[Multiclock] Add clock fields to Bridges; update FCCAs to target them
2019-11-01 11:29:58 -07:00
dd724e217b
Match FCCAs with or without clocks
2019-10-30 17:59:52 -07:00
ab4d4a04ac
[WIP] [WIP] Rational clock bridge
2019-10-30 17:23:29 -07:00
ae6c22115f
Construct FCCAs using new factory methods
2019-10-30 17:21:16 -07:00
2bc44adeaa
Add clock field to FCCA, add ClockChannel info type
2019-10-30 16:07:05 -07:00
c8f5af8e50
Inline the MIDAS submodule
2019-10-18 18:03:19 +00:00
d2c3552c35
Bump MIDAS
2019-10-12 05:03:08 +00:00
d5eaddb06d
Update runtime config generation to use a new stage
2019-10-10 02:18:05 +00:00
a1f3a927a9
Rename Endpoint -> Bridge
2019-10-06 03:35:03 +00:00
9bd6679ea8
Serializable Endpoints & Golden Gate as a Stage
2019-10-04 22:43:46 -07:00
4c1a3aa212
Update build recipes to reflect new config organization
2019-10-04 18:28:19 +00:00
9ca73689af
Merge remote-tracking branch 'origin/dev' into midas2-endpoint-rework
2019-09-19 09:42:50 -07:00
9edf0b86a7
Bump MIDAS to let IsEndpoint mix into BaseModules
2019-09-17 11:49:53 -07:00
d794bbb5e9
Bump MIDAS and update FASEDtests
2019-09-17 11:40:38 -07:00
6e56ad2bed
Bump MIDAS; HostPort moved into widgets
2019-09-13 00:32:11 -07:00
a61d42b1c8
Bump chipyard and midas to dev
2019-09-13 00:21:37 +00:00
3b8cb231c8
Bump MIDAS; FASEDEndpoint use in AXI4 Fuzzer
2019-09-07 17:47:43 -07:00
d24f8cc6d9
Update endpoint definitions
2019-09-06 12:14:39 -07:00
17a95ef2d4
Bump MIDAS; note token backpressure hack ( #335 )
2019-08-29 04:20:31 +00:00
d6a802135a
Merge remote-tracking branch 'origin/midas2' into midas2-endpoint-rework
2019-08-19 11:17:36 -07:00
35b0be7c7f
Merge remote-tracking branch 'origin/dev' into midas2
2019-08-16 19:19:09 +00:00
e5feeda548
Bump MIDAS for variable renaming
2019-07-24 21:46:23 +00:00
341a538b6f
Merge 'origin/master' into dev for blkdev fix; bump midas
2019-07-23 23:19:34 +00:00
895fb37d2d
Add +vcs+initmem+0; add the vcs args to the .d-derived MLSim targets
2019-07-23 15:41:38 -07:00
a3d48a43a9
Bump midas for channel name changes
2019-07-23 21:59:58 +00:00
c7784c60d2
Merge remote-tracking branch 'origin/dev' into midas2
2019-07-23 21:10:30 +00:00
78fdff25af
Update MACRO names :(
2019-07-12 19:50:55 -07:00
0aa7ff93c7
Bring up Printf Synthesis
2019-07-12 16:44:20 -07:00
448eae5f4f
Bring up assertion synthesis
2019-07-12 16:00:49 -07:00
be6bc69abd
Update MemModelKey to use Endpoint; bring up FASEDtests
2019-07-12 14:50:15 -07:00
765e2ab144
Update all MIDAS examples to use BlackBox endpoints
2019-07-12 11:02:54 -07:00
1c7f6a99ea
have midas support memory channels with different address widths
2019-07-11 15:14:11 -07:00
62ea9e5fc2
Update endpoint IO definitions; include tReset in HostPorts
2019-07-10 22:31:37 -07:00
8718224132
[WIP] Black box-based endpoint rework; GCD simulates
2019-07-09 17:46:43 -07:00
7f8152e511
Bump MIDAS to dev
2019-06-28 23:51:58 +00:00
40ca9c71ac
Merge remote-tracking branch 'origin/dev' into firesim-as-a-library
2019-06-28 04:57:46 +00:00
c91aba2252
Bump MIDAS for new RV channel implementation
2019-06-27 17:55:07 -07:00
5c2aaa3f64
Merge submodule dev branches into master; bump
2019-06-26 22:41:23 +00:00
29b905c2b3
Initialize channels with tokens to improve FMR
2019-06-24 11:53:30 -07:00
503d2135c5
Fix TracerV test
2019-06-21 17:18:33 -07:00
6147071b1f
[M2] Readd a lost config, and bump
2019-06-20 23:46:33 +00:00
2d2cb5db73
Bump MIDAS
2019-06-20 16:41:35 +00:00
0b3bba7324
Get RiscSRAM working again
2019-06-20 01:12:54 +00:00
c11eb9f1ee
Pull in firesim dev; most of the midas examples work
2019-06-19 23:34:23 +00:00
40965603a0
Bump firesim, WIP
2019-06-19 22:09:02 +00:00
d3c4930a2c
ICCAD submission
2019-06-19 19:23:05 +00:00
0205a85d18
Major reorganization to enable FireSim-as-a-library
2019-05-29 00:48:03 +00:00
b8d1ea3f6f
Add a finish method to all endpoints and call it
2019-05-24 17:33:55 +00:00
db94bdc244
Bump RC once more; fix diplomatic trace handling
2019-05-16 19:07:06 +00:00
33086134fe
WIPCITY
2019-05-11 07:19:54 +00:00
e8e9fd1ee4
Bump MIDAS and publish AGFIs
2019-04-25 21:35:33 +00:00
5da102e56c
Add support for runtime configurable MSHRs in FASED LLC models
2019-04-24 19:38:04 +00:00
42353ab8d5
Get ram-replacement working for RiscSRAM
2019-03-29 00:20:18 +00:00
70ba9dd058
Bump midas
2019-03-26 17:17:45 -07:00
9ac4065e49
Actually bump midas
2019-03-26 23:56:42 +00:00
12e9d10a47
Enable port annotation generation
2019-03-26 19:22:45 +00:00
88bc426ff5
bump to midas master
2019-02-24 16:43:44 -08:00
1d7f5607c5
Bump midas
2019-02-18 04:00:42 +00:00
773a29e66c
Update more names, purge software memory model
2019-02-17 14:21:10 -08:00
6beec9f4bd
Update references to FASED; Add scalatests
2019-02-16 22:25:53 -08:00
71c04a5c96
Bump MIDAS
2019-02-13 22:36:09 +00:00
cd77c1bd93
Bump MIDAS for RVChannel non-determinism fixes
2019-02-11 05:09:19 +00:00
1f298f5a18
Bump midas to dev
2019-02-07 01:54:33 +00:00
dc1537ad50
[print] Update plusargs to synthesized printf driver
2019-02-04 15:37:21 -08:00
22a70aa26f
Bump MIDAS for verilator lint rule fixes
2019-01-22 21:56:35 +00:00
76d38433e0
Add ram model annotations to boom and rocket RFs; add tests
2019-01-22 19:50:56 +00:00
c6ad5ff011
Bump MIDAS to head of dev
2019-01-20 01:33:18 +00:00
f04c282ebf
Bump MIDAS
2019-01-19 04:49:46 +00:00
4c24c4175f
Bump midas and update docs for improved FpgaDebug annotator
2019-01-19 00:05:38 +00:00
fcce6d4a17
[print] Update printfile plusarg to be consistent
2019-01-17 01:29:38 +00:00
1511828f01
Bump midas
2019-01-15 17:32:19 +00:00
196140105f
Remove branch-specific FIRRTL features, bump FIRRTL to master
2019-01-03 20:50:19 -08:00
3df039b6ea
Bump midas for TopWiringAnno fix
2018-12-28 15:24:11 +00:00
5595dbb785
[print] Add cases for the bugs Albert encountered
2018-12-20 16:26:21 +00:00
ce909c1fbe
Bump midas
2018-12-15 16:42:58 -08:00
c50dd9ebfc
[Print] Enable token compression
2018-12-15 16:31:55 -08:00
1073f6b759
[print] Add a midasexample that packs narrow printf tokens
2018-12-15 14:06:47 -08:00
e7825e7962
[print] Diff logs in scalatest
2018-12-15 12:14:29 -08:00
30507d49f6
[print] Add a (currently failing) test to diff output
2018-12-14 08:41:06 +00:00
0c01768611
Bump midas
2018-12-14 08:38:27 +00:00
af6b3f6bf1
[print] Bring up printSynth in rocket
2018-12-14 08:37:38 +00:00
70f093fd8c
[Driver] Properly invoke endpoint dtors
2018-12-14 08:37:02 +00:00
b64b87f5fb
[Print] Support synthesized printfs that exceed DMA width
2018-12-14 08:35:43 +00:00
886c987210
[midasexamples] Update initialization and teardown of print widget
2018-12-14 08:35:11 +00:00
249ab27082
[midasexamples] Add print plusargs
2018-12-14 08:34:16 +00:00
0dc7f528ee
[midasexamples] Properly instantiate print endpoint
2018-12-14 08:33:12 +00:00
981fddbde0
[WIP] Add a failing PrintModule midas example
2018-12-14 08:23:14 +00:00
3ee77b8fac
Bump midas
2018-12-12 22:22:05 +00:00
525c7d1a43
Use annotation to extract SRAM in RiscSRAM example
2018-12-10 15:52:44 -08:00
44344c69c0
Move MIDAS 2.0 passes out of FIRRTL
2018-12-09 00:25:35 -08:00
0f8796eb39
[endpoints] Bump midas, update Endpoint imports
2018-12-07 16:38:07 -08:00
2a5a1183e5
[endpoints] Bump MIDAS, use DMA mixins in NIC
2018-12-07 14:13:15 -08:00
3801a855cc
Merge remote-tracking branch 'origin/dev' into multiclock-fame
2018-12-04 11:21:18 -08:00
3b556842fa
[SBT] Manage FIRRTL dependency manually; add a midas targetutils package
...
This fixes two major limitations:
- stops using local maven to host the FIRRTL dependency
- creates an upstream project to hold MIDAS's target-land annotations,
that can be used in RC (breaking the existing circular dep.)
2018-11-30 12:45:37 -08:00
e596054970
bump aws-fpga and midas
2018-11-30 18:40:31 +00:00
84f453d754
bump midas
2018-11-30 06:22:51 +00:00
02dbb5228d
Bump midas/firrtl to do SRAM model extraction
2018-11-28 11:40:51 -08:00
7da28256da
Merge remote-tracking branch 'origin/dev' into supernode-integration
2018-11-27 03:12:17 +00:00
e6ca17a1c3
Bump midas, firrtl, change simpleNIC reset token handling
2018-11-26 18:40:27 -08:00
fafb3ab8cb
Add MIDAS address range counters
2018-11-27 01:17:31 +00:00
c246edc7da
Bring up annotation-driven channel generation
2018-11-26 11:56:33 -08:00
c643db10e1
bump midas
2018-11-21 18:02:46 -08:00
0f436c3f53
[WIP] Update peek poke semantics, add interconnect ME
2018-11-21 16:04:26 -08:00
670e1a2ca7
bump midas
2018-11-19 21:29:28 +00:00
0a3524d761
auto-generate DMA address map instead of hard-coding
2018-11-19 21:26:17 +00:00
e49b24feaf
Bump MIDAS
2018-11-19 13:25:11 -08:00
6b81a128f6
Merge remote-tracking branch 'origin/dma-addr-auto-assign' into supernode-integration
2018-11-19 21:12:41 +00:00
54d0d94f07
[endpoints] More autoclonetype fixes
2018-11-18 22:38:23 -08:00
2ac24f9ccf
bump midas
2018-11-17 21:34:58 +00:00
80f84903f6
auto-generate DMA address map instead of hard-coding
2018-11-17 18:09:40 +00:00
6104af98e8
bump midas dev
2018-11-16 21:37:57 +00:00
a5616eb5c3
Switch to using XDMA instead of EDMA. One catch is that we always have
...
to flash all of the FPGAs on an instance, otherwise XDMA hangs. See
comment in run_farm.py. See performance results below:
latency
--------
old (edma):
[[0.021875, 2.05], [0.5009374999999999, 21.78], [0.9996875, 26.3], [2.0015625, 29.14], [2.9990625, 30.26], [4.0009375, 30.91], [5.000624999999999, 31.92], [6.0003125, 32.87], [7.0, 33.11], [7.9996875, 34.01], [8.999375, 34.03], [9.999062499999999, 34.31]]
new (xdma):
[(0.021875, 2.39), (0.5009374999999999, 26.13), (0.9996875, 31.41), (2.0015625, 35.97), (2.9990625, 37.85), (4.0009375, 38.98), (5.000624999999999, 39.71), (6.0003125, 40.17), (7.0, 40.39), (7.9996875, 40.72), (8.999375, 40.75), (9.999062499999999, 40.89)]
scale (truncated)
-------
old (edma):
[(64, 8.84), (32, 27.54), (16, 28.77), (8, 29.74), (4, 33.32), (2, 35.4), (1, 37.02)]
new (xdma):
[(64, 9.3), (32, 34.58), (16, 35.06), (8, 35.93), (4, 40.09), (2, 43.1), (1, 44.49)]
2018-11-16 20:19:08 +00:00
4d9e432c39
[Endpoints] Change how the host memory offset is generated
2018-11-15 01:19:29 -08:00
2b3bfc05e1
bump midas and aws-fpga
2018-11-15 04:57:55 +00:00
49ae13f2db
bump to MIDAS master
2018-11-13 21:55:45 +00:00
eed7f15c86
bump midas
2018-11-08 07:51:05 +00:00
fc2d3b8c52
bump midas
2018-11-08 05:44:00 +00:00
dc4305ef2e
Merge branch 'dev' of https://github.com/firesim/firesim into supernode-integration
2018-11-08 05:43:19 +00:00
2647895253
bump midas to dev
2018-11-08 04:24:58 +00:00
4d8dfd6e37
convert assertion widget to structs
2018-11-08 02:09:24 +00:00
cfb1df03b4
bump aws-fpga and midas supernode-integration
2018-11-08 00:28:57 +00:00
292493711e
bump midas with merge commit
2018-11-06 23:05:33 +00:00
f50e7812b0
Merge remote-tracking branch 'origin/dev' into eliminate-macros
2018-11-06 22:49:20 +00:00
6494b54faa
Bump midas to dev
2018-11-06 22:00:52 +00:00
40edaa59e1
bump midas
2018-11-06 18:10:45 +00:00
0ec0d6b7ea
Merge remote-tracking branch 'origin/dev' into assertion-synthesis
2018-11-05 20:31:34 +00:00
af7fc34aa8
example of having multiple blkdev widgets in firesim_top.cc
2018-11-05 20:00:09 +00:00
72a614e7a5
port over more widgets to structs rather than macros
2018-11-05 00:09:56 +00:00
793a5ebc37
convert master to struct
2018-11-04 22:36:49 +00:00
1a84d4ad9f
Disable assertion synthesis by default in MIDAS
2018-11-01 19:34:49 +00:00
e03f4fd676
Merge remote-tracking branch 'origin/dev' into assertion-synthesis
2018-10-31 19:37:50 -07:00
994fedcad8
Bump MIDAS for exit_code bugfix
2018-10-31 19:32:08 -07:00
4e6e517745
Add assertion endpoint to firesim's driver
2018-10-31 19:05:34 -07:00
190ac2f5e1
[midasexamples] Add a child module to AssertModule
2018-10-31 18:43:33 -07:00
dfb6fa3620
Bring up assertion synthesis in MIDAS-level simulation
2018-10-31 17:58:29 -07:00
e04e9dd632
new structs work for simplenic
2018-10-31 17:36:58 +00:00
ca94d7fa20
switch simplenic to struct instead of macros
2018-10-30 00:29:15 +00:00
ddfc91019b
PASSES ALL ASM TESTS!
...
But peek/poke for decoupledIO is busted. Breaks pointerchaser.
2018-10-14 04:54:58 -07:00
feb399bd33
Merge remote-tracking branch 'origin/dev' into multiclock-fame
2018-10-13 17:48:38 -07:00
5c3fb37e3d
Bump firrtl, midas, don't remove debugio
2018-10-13 17:40:56 -07:00
1ab15cd964
Make pointerchaser actually work
2018-10-12 18:57:38 -07:00
af6eba7d81
Bump midas to dev
2018-10-12 18:31:33 +00:00
2ab3e0218c
Merge remote-tracking branch 'origin/dev' into multiclock
2018-10-11 17:48:10 +00:00
ce57342a23
Bump midas, firrtl
2018-10-09 14:06:47 -07:00
0f241d32bd
WIP - Serious hacking on SimWrapper and channel handling
2018-10-07 22:38:51 -07:00
b8f9c49a26
fix midas LOADMEM issues
2018-10-05 22:07:06 +00:00
fc13e7597c
Update generators to pass Seq[(String, Data)] to midas.Compiler
...
Also promote BRAMQueue to MIDAS
2018-10-03 20:01:30 -07:00
7cee7d15a9
updated commit of midas
2018-09-29 04:19:32 +00:00
211bf0041c
Bump midas and update unittest recipes
2018-09-28 11:59:30 -07:00
00bf4d07dd
Merge branch 'dev' into dev-tracerv
2018-09-28 04:45:49 +00:00
b28259fbda
fix NASTI problems
2018-09-28 01:24:19 +00:00
b32217a0ef
bump to midas dev
2018-09-27 00:12:03 +00:00
03caa08ded
Merge remote-tracking branch 'origin/dev' into bump-again-maybe
2018-09-26 20:55:49 +00:00
a3c354c9e5
passes asm tests (does not exclude boom yet, see next commit)
2018-09-26 20:47:41 +00:00
9505b5a7e4
Bump midas to dev
2018-09-26 18:27:20 +00:00
0bac978f98
Merge remote-tracking branch 'origin/dev' into multiclock
2018-09-24 15:54:34 -07:00
16bd052b34
Bump midas
2018-09-24 22:24:39 +00:00
313dfb0fad
More fesvr cleanup; allow any endpoint to bring down simulation
2018-09-24 21:59:58 +00:00
39c97c42b3
Merge branch 'dev' into dev-tracerv
2018-09-24 04:08:39 +00:00
7628ca0214
point midas to dev
2018-09-23 18:54:57 +00:00
33502b7e3a
allow NIC and TraceRV to both be active
2018-09-23 18:22:07 +00:00
fe29356d89
start bumping submodules
2018-09-22 23:51:29 +00:00
8b2718cb62
bump midas to master
2018-09-22 21:57:35 +00:00
9bb2f0ccf7
bump midas to dev branch
2018-09-20 21:40:05 +00:00
7572e77cfa
Bump MIDAS once more
2018-09-19 18:06:52 -07:00
0bff2d4fd7
bump submodules
2018-09-19 15:59:42 +00:00
df3045e06b
Move ILAWiringPass into FireSim
2018-09-17 22:06:56 -07:00
bad01d4140
Merge branch 'dev' of https://github.com/firesim/firesim into auto-ila
2018-09-12 23:34:03 +00:00
a1d19f9d0d
bump midas and aws-fgpa to auto-ila
2018-09-12 22:40:24 +00:00
66f4a5dce7
Makefile rework & partial introduction of MIDAS examples
2018-08-25 20:54:39 +00:00
442d3cc5d8
[Driver] Make read_chunk bypass to loadmem during program load
...
For programs that were not aligned to 32 bytes, fesvr would attempt
to read that chunk before writing out the last chunk of the program.
This read would not bypass to loadmem -- it would fetch a
line into cache -- however, the final write would bypass to DRAM, leaving
the line in outer cache that would not be invalidated.
2018-08-05 00:59:09 -07:00
1b06a6e2aa
Bump midas; Add a switch to zero out dram with loadmem
2018-08-02 00:00:41 -07:00
67b1f9766c
Add recipes for running MIDAS unittests
2018-07-23 13:33:47 -07:00
5ef36167d9
Support for integer clock division between RC and endpoints
2018-07-18 19:19:24 -07:00
e488c9c0ff
fix F1 verilator harness
2018-06-10 03:08:00 +00:00
c06711d73f
Bump RC, Midas, Chisel -> 3.1, Firrtl -> 1.2, renable BOOM (NoNIC)
2018-05-16 16:43:05 +00:00
bba9dea481
New squashed FireSim repo for open-sourcing
...
This is the new FireSim repo that will be open-sourced. This commit
matches the state of the repo at commit
031132485840608f111e6c745d8140b5def6d857 of the original FireSim
repo, which now lives at
https://github.com/firesim/firesim-prerelease
All future FireSim development will happen in this repository. The
FireSim pre-release repo is maintained privately only for archival
purposes (e.g. if someone needs to do git blame on a file) - no new
commits should be made on the pre-release repo.
2018-05-13 19:40:34 +00:00
David Biancolin