Merge remote-tracking branch 'origin/dev' into firesim-as-a-library
This commit is contained in:
commit
40ca9c71ac
43
CHANGELOG.md
43
CHANGELOG.md
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@ -2,6 +2,49 @@
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This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
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## [1.6.0] - 2019-06-23
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/firesim/firesim/pull/262
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The primary change in this release is a Rocket-Chip bump in FireChip and associated submodules (Chisel, FIRRTL, RISC-V tools)
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The release also updates firesim-software, see the changelog at sw/firesim-software/CHANGELOG.md for details (PR #303).
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### Added
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* PR #250. Add support for flow control via Ethernet pause frames.
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* PR #280. Add support for a FIRESIM_RUNFARM_PREFIX env var to differentiate between runfarms for multiple clones of firesim.
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* Resolves #263
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* PR #286 Add support for arbitrary host frequency selection (by synthesizing a new PLL).
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* Resolves #252
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* PR #287 Add support for runtime-configurable MSHR in FASED
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* PR #290 Add endpoint::finish() to let endpoints run code before simulation teardown
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* firesim-software PR firesim/firesim-software#31 allows firesim-software to work outside of a firesim environment without the need for sudo (just riscv-tools, qemu, and a few package requirements).
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### Changed
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* PR #261 Print out that post run hook is running, so it doesn't look like simulation termination is stuck.
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* PR #290 Bumps RocketChip from 50bb13d (Sept 25th, '18) to b8baef6 (May 10th, '19)
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* Bumps Buildroot in firesim-software; points at upstream
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* Bumps RISC-V tools; RISC-V toolchain is built directly from build-setup.sh
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* Resolves #217
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* Enables TracerV support by default
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* firesim-software PR firesim/firesim-software#25 updates buildroot to a more recent version in order to support a more recent version of riscv-tools to match the updated tools in this firesim release.
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### Fixed
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* PR #275. Fix small root volume size for build instances.
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* Increased to 200GB
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* Resolves #274
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* Resolves #265
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* PR #287 Fixes FASED LLC timing model bug.
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* PR #301 Fixes a bug in synthesizable printf cycle prefixes
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### Deprecated
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* None
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### Removed
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* None
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### Security
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* None
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## [1.5.0] - 2019-02-24
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A more detailed account of everything included is included in the dev->master PR for this release: https://github.com/firesim/firesim/pull/168
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@ -105,7 +105,7 @@ fi
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if [ "$FASTINSTALL" = "true" ]; then
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git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git
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cd firesim-riscv-tools-prebuilt
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git checkout 85eb89490a730915a28eca3c25d4496193951565
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git checkout 5fee18421a32058ab339572128201f4904354aaa
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PREBUILTHASH="$(cat HASH)"
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cd $target_toolchain_dir
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git submodule update --init riscv-tools
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@ -138,15 +138,31 @@ else
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git submodule update --init --recursive riscv-tools #--jobs 8
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cd riscv-tools
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export MAKEFLAGS="-j16"
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./build.sh
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# Copied from riscv-tools build.sh
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source build.common
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echo "Starting RISC-V Toolchain build process"
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build_project riscv-fesvr --prefix=$RISCV
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build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV
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build_project riscv-gnu-toolchain --prefix=$RISCV
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CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv64-unknown-elf
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build_project riscv-tests --prefix=$RISCV/riscv64-unknown-elf
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echo -e "\\nRISC-V Toolchain installation completed!"
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# build static libfesvr library for linking into driver
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cd riscv-fesvr/build
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$RDIR/scripts/build-static-libfesvr.sh
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# build linux toolchain
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cd $RDIR
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# build linux toolchain
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cd $target_toolchain_dir/riscv-tools/riscv-gnu-toolchain/build
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make -j16 linux
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cd $RDIR
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# build QEMU
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cd sw/qemu
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./configure --target-list=riscv64-softmmu --prefix=$RISCV
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make -j16
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make install
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cd $RDIR
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fi
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echo "export FIRESIM_ENV_SOURCED=1" > env.sh
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cd "$RDIR/platforms/f1/aws-fpga/sdk/linux_kernel_drivers/xdma"
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make
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# Install firesim-software python libraries
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# Install firesim-software dependencies
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cd $RDIR
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sudo pip3 install -r sw/firesim-software/python-requirements.txt
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cat sw/firesim-software/centos-requirements.txt | sudo xargs yum install -y
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# run sourceme-f1-full.sh once on this machine to build aws libraries and
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# pull down some IP, so we don't have to waste time doing it each time on
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@ -39,7 +39,7 @@ class BuildConfig:
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{
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'DeviceName': '/dev/sda1',
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'Ebs': {
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'VolumeSize': 100,
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'VolumeSize': 200,
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'VolumeType': 'gp2',
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},
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},
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@ -10,32 +10,32 @@
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# own images.
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[fireboom-singlecore-nic-ddr3-llc4mb]
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agfi=agfi-04fbd4e1e16e9cc06
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agfi=agfi-03e6e564659bd0aed
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deploytripletoverride=None
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customruntimeconfig=None
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[fireboom-singlecore-no-nic-ddr3-llc4mb]
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agfi=agfi-067142e76de97dcb4
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agfi=agfi-0459cfa6dad378686
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deploytripletoverride=None
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customruntimeconfig=None
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[firesim-quadcore-nic-ddr3-llc4mb]
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agfi=agfi-0ee9ea5b27c928b58
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agfi=agfi-0c745f8af725cf074
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deploytripletoverride=None
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customruntimeconfig=None
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[firesim-quadcore-no-nic-ddr3-llc4mb]
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agfi=agfi-0612f9e6c22bc6448
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agfi=agfi-00cedc0b7d4ccc9a6
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deploytripletoverride=None
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customruntimeconfig=None
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[firesim-singlecore-no-nic-lbp]
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agfi=agfi-0beded186d46e6c90
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agfi=agfi-0dd065a67365f8a56
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deploytripletoverride=None
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customruntimeconfig=None
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[firesim-supernode-singlecore-nic-lbp]
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agfi=agfi-0efd582a3bfcf11b4
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agfi=agfi-0b168a3effc91fc4a
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deploytripletoverride=None
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customruntimeconfig=None
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@ -48,11 +48,15 @@ Using the ILA at Runtime
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Prerequisite: Make sure that ports 3121 and 10201 are enabled in the firesim AWS security group.
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In order to use the ILA, we must enable the GUI interface on our manager instance.
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This can be done by running the command:
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This can be done by running the following commands:
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::
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curl https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Scripts/setup_gui.sh -o /home/centos/src/scripts/setup_gui.sh
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sudo sed -i 's/enabled=0/enabled=1/g' /etc/yum.repos.d/CentOS-CR.repo
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/home/centos/src/scripts/setup_gui.sh
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# keep manager paramiko compatibility
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sudo pip2 uninstall gssapi
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When the command will finish running, a temporary password will be printed out. This
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password will be used to access the GUI interface of the master instance. We will
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class FireSimRocketChipQuadCoreTracedConfig extends Config(
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new WithTraceRocket ++ new FireSimRocketChipQuadCoreConfig)
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In SimConfigs.scala:
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.. code-block:: scala
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class FireSimDDR3FRFCFSLLC4MBConfig extends Config(
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new WithSerialWidget ++
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new WithUARTWidget ++
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new WithSimpleNICWidget ++
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new WithBlockDevWidget ++
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new FRFCFS16GBQuadRankLLC4MB ++
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new WithTracerVWidget ++ // <--- add this
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new BasePlatformConfig)
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In config_build_recipes.ini:
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.. code-block:: ini
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This process will take about 10 to 15 minutes on a ``c4.4xlarge`` instance.
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Once this is completed, you'll have the following files:
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- ``firesim/sw/firesim-software/images/br-disk-bin`` - a bootloader + Linux
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- ``firesim/sw/firesim-software/images/br-base-bin`` - a bootloader + Linux
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kernel image for the nodes we will simulate.
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- ``firesim/sw/firesim-software/images/br-disk.img`` - a disk image for
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- ``firesim/sw/firesim-software/images/br-base.img`` - a disk image for
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each the nodes we will simulate
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These files will be used to form base images to either build more complicated
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runfarmtag=mainrunfarm
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f1_16xlarges=0
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f1_4xlarges=1
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f1_4xlarges=0
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m4_16xlarges=0
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f1_2xlarges=1
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@ -52,8 +52,6 @@ sudo pip2 install graphviz==0.8.3
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sudo pip2 install --upgrade --ignore-installed pyparsing
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sudo pip2 install matplotlib==2.2.2
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sudo pip2 install pandas==0.22.0
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# this is explicitly installed to downgrade it to a version without deprec warnings
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sudo pip2 install cryptography==2.2.2
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# new awscli on 1.6.0 AMI is broken with our versions of boto3
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sudo pip2 install awscli==1.15.76
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@ -1 +1 @@
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Subproject commit e3f0e7f538dc49d6eb86c3528b52cdbf53237417
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Subproject commit daf665bbe14a0e3f775b9a2e000ae37409d00f3f
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@ -87,18 +87,27 @@ verilator_debug = $(GENERATED_DIR)/V$(DESIGN)-debug
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vcs = $(GENERATED_DIR)/$(DESIGN)
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vcs_debug = $(GENERATED_DIR)/$(DESIGN)-debug
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xsim = $(GENERATED_DIR)/$(DESIGN)-$(PLATFORM)
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sim_binary_basename := $(basename $(notdir $(SIM_BINARY)))
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run-verilator: $(verilator)
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$(verilator) +permissive $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY))
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cd $(dir $<) && \
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$(verilator) +permissive $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY)) \
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$(disasm) $(sim_binary_basename).out
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run-verilator-debug: $(verilator_debug)
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$(verilator_debug) +permissive $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY))
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cd $(dir $<) && \
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$(verilator_debug) +permissive +waveform=$(sim_binary_basename).vpd $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY)) \
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$(disasm) $(sim_binary_basename).out
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run-vcs: $(vcs)
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$(vcs) +permissive $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY))
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cd $(dir $<) && \
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$(vcs) +permissive $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY)) \
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$(disasm) $(sim_binary_basename).out
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run-vcs-debug: $(vcs_debug)
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$(vcs_debug) +permissive $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY))
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cd $(dir $<) && \
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$(vcs_debug) +permissive +waveform=$(sim_binary_basename).vpd $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY)) \
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$(disasm) $(sim_binary_basename).out
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run-xsim: $(xsim)
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cd $(dir $<) && ./$(notdir $<) +permissive $(COMMON_SIM_ARGS) $(FPGA_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \
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@ -1 +1 @@
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Subproject commit e5e04f0668793340947ae740474d0768b0bda42c
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Subproject commit 389c3df8f3d5e3548c46feb2d63be700c89a15ec
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@ -1 +1 @@
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Subproject commit f4fb0c42b1e547dfa815b225b482166b92743de5
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Subproject commit 8700ff05e57ca6d88b1eeff50418dddd66fa0ccb
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