[gg] Remove legacy Compiler object; use phase only

sim/midas/src/main/scala/midas/Compiler.scala

@@ -45,46 +45,3 @@ private class LastStageVerilogCompiler extends firrtl.Compiler {
   def transforms = Seq(new firrtl.LowFirrtlOptimization,
                        new firrtl.transforms.RemoveReset)
 }
-
-object MidasCompiler {
-  def apply(
-      chirrtl: Circuit,
-      targetAnnos: Seq[Annotation],
-      io: Seq[(String, Data)],
-      dir: File,
-      targetTransforms: Seq[Transform], // Run pre-MIDAS transforms, on the target RTL
-      hostTransforms: Seq[Transform]    // Run post-MIDAS transformations
-    )
-     (implicit p: Parameters): CircuitState = {
-    val midasAnnos = Seq(
-      firrtl.TargetDirAnnotation(dir.getPath()),
-      InferReadWriteAnnotation)
-    val midasTransforms = new passes.MidasTransforms(io)(p alterPartial { case OutputDir => dir })
-    val compiler = new MidasCompiler
-    val midas = compiler.compile(firrtl.CircuitState(
-      chirrtl, firrtl.ChirrtlForm, targetAnnos ++ midasAnnos),
-      targetTransforms :+ midasTransforms)
-
-    val postHostTransforms = new HostTransformCompiler().compile(midas, hostTransforms)
-    val result = new LastStageVerilogCompiler().compileAndEmit(postHostTransforms)
-
-    writeEmittedCircuit(result, new File(dir, s"FPGATop.v"))
-    result
-  }
-
-  // Unlike above, elaborates the target locally, before constructing the target IO Record.
-  def apply[T <: chisel3.core.UserModule](
-      w: => T,
-      dir: File,
-      targetTransforms: Seq[Transform] = Seq.empty,
-      hostTransforms: Seq[Transform] = Seq.empty
-    )
-     (implicit p: Parameters): CircuitState = {
-    dir.mkdirs
-    lazy val target = w
-    val circuit = chisel3.Driver.elaborate(() => target)
-    val chirrtl = firrtl.Parser.parse(chisel3.Driver.emit(circuit))
-    val io = target.getPorts map (p => p.id.instanceName -> p.id)
-    apply(chirrtl, circuit.annotations.map(_.toFirrtl), io, dir, targetTransforms, hostTransforms)
-  }
-}