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[gg] Also check for clock ports in EnsureNoTargetIO.scala

This commit is contained in:
David Biancolin 2019-11-19 22:58:21 -08:00
parent e407176a7c
commit 8aeed3484a
1 changed files with 14 additions and 6 deletions
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20
sim/midas/src/main/scala/midas/passes/EnsureNoTargetIO.scala
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@ -18,6 +18,8 @@ import java.io.{File, FileWriter, StringWriter}
// Ensures that there are no dangling IO on the target. All I/O coming off the DUT must be bound
// to an Bridge BlackBox
case class TargetMalformedException(message: String) extends RuntimeException(message)
private[passes] class EnsureNoTargetIO extends firrtl.Transform {
def inputForm = HighForm
def outputForm = HighForm
@ -27,14 +29,20 @@ private[passes] class EnsureNoTargetIO extends firrtl.Transform {
val topName = state.circuit.main
val topModule = state.circuit.modules.find(_.name == topName).get
val nonClockPorts = topModule.ports.filter(_.tpe != ClockType)
val (clockPorts, nonClockPorts) = topModule.ports.partition(_.tpe == ClockType)
if (!clockPorts.isEmpty) {
val exceptionMessage = "Your target design has the following unexpected clock ports:\n" +
clockPorts.map(_.name).mkString("\n") +
"\nRemove these ports and generate clocks for your simulated system using a ClockBridge."
throw TargetMalformedException(exceptionMessage)
}
if (!nonClockPorts.isEmpty) {
val exceptionMessage = """
Your target design has dangling IO.
You must bind the following top-level ports to an Bridge BlackBox:
""" + nonClockPorts.map(_.name).mkString("\n")
throw new Exception(exceptionMessage)
val exceptionMessage = "Your target design has the following unexpecte IO ports:\n" +
nonClockPorts.map(_.name).mkString("\n") +
"\nRemove these ports and instead bind their sources/sinks to a target-to-host Bridge."
throw TargetMalformedException(exceptionMessage)
}
state
}