[gg] Fix assert pass under no assertions
This commit is contained in:
David Biancolin
parent
200b0e81c8
commit
6c6c209589
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@ -180,69 +180,66 @@ private[passes] class AssertPass(
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val mods = postorder(c, meta)(wireSynthesizedAssertions(meta, CircuitTarget(c.main)))
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val formattedMessages = formatMessages(meta, c.main)
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// Step 4: Associate each assertion with a source clock
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val mInfo = new ModuleAssertInfo(topModule, meta, topMT)
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val postWiredState = state.copy(circuit = c.copy(modules = mods), form = MidForm)
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val loweredState = Seq(new ResolveAndCheck, new HighFirrtlToMiddleFirrtl, new MiddleFirrtlToLowFirrtl).foldLeft(postWiredState)((state, xform) => xform.transform(state))
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val clockMapping = FindClockSources(loweredState, mInfo.allClocks)
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val rootClocks = mInfo.allClocks.map(clockMapping)
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// For each clock in clock channel, list associated assert indices
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val groupedAsserts = rootClocks.zipWithIndex.groupBy(_._1).mapValues(values => values.map(_._2))
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// Step 5: Re-wire the top-level module
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val ports = collection.mutable.ArrayBuffer[Port]()
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val stmts = collection.mutable.ArrayBuffer[Statement]()
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val assertAnnos = collection.mutable.ArrayBuffer[Annotation]()
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// Step 5a: Connect all assertions to a single wire to match the order of our previous analysis
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val allAssertsWire = DefWire(NoInfo, "allAsserts", mInfo.assertUInt)
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val allAssertConnect = Connect(NoInfo, WRef(allAssertsWire), cat(mInfo.allAsserts.reverse))
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stmts ++= Seq(allAssertsWire, allAssertConnect)
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// Step 5b: Generate unique ports for each clock
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for ((clockRT, asserts) <- groupedAsserts) {
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val portName = namespace.newName(s"midasAsserts_${clockRT.ref}")
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val clockPortName = namespace.newName(s"midasAsserts_${clockRT.ref}_clock")
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val tpe = UIntType(IntWidth(asserts.size))
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val port = Port(NoInfo, portName, Output, tpe)
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val clockPort = Port(NoInfo, clockPortName, Output, ClockType)
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ports ++= Seq(port, clockPort)
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val bitExtracts = asserts.map(idx => DoPrim(PrimOps.Bits, Seq(WRef(allAssertsWire)), Seq(idx, idx), UIntType(IntWidth(1))))
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val connectAsserts = Connect(NoInfo, WRef(port), cat(bitExtracts.reverse))
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val connectClock = Connect(NoInfo, WRef(clockPort), WRef(clockRT.ref))
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stmts ++= Seq(connectClock, connectAsserts)
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// Generate the bridge Annotation
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val portRT = ModuleTarget(c.main, c.main).ref(portName)
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val clockPortRT = ModuleTarget(c.main, c.main).ref(clockPortName)
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val fcca = FAMEChannelConnectionAnnotation.source(portName, WireChannel, Some(clockPortRT), Seq(portRT))
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val assertMessages = asserts.map(formattedMessages(_))
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val bridgeAnno = BridgeIOAnnotation(
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target = portRT,
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widget = Some((p: Parameters) => new AssertBridgeModule(assertMessages)(p)),
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channelMapping = Map("" -> portName)
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)
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assertAnnos ++= Seq(fcca, bridgeAnno)
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}
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val wiredTopModule = topModule.copy(ports = topModule.ports ++ ports,
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body = Block(topModule.body +: stmts.toSeq))
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println(s"[Golden Gate] total # of assertions synthesized: ${mInfo.assertWidth}")
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state.copy(
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circuit = c.copy(modules = wiredTopModule +: mods.filterNot(_.name == c.main)),
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form = HighForm,
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annotations = state.annotations ++ assertAnnos
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)
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if (!mInfo.hasAsserts) state else {
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// Step 4: Associate each assertion with a source clock
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val postWiredState = state.copy(circuit = c.copy(modules = mods), form = MidForm)
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val loweredState = Seq(new ResolveAndCheck, new HighFirrtlToMiddleFirrtl, new MiddleFirrtlToLowFirrtl).foldLeft(postWiredState)((state, xform) => xform.transform(state))
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val clockMapping = FindClockSources(loweredState, mInfo.allClocks)
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val rootClocks = mInfo.allClocks.map(clockMapping)
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// For each clock in clock channel, list associated assert indices
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val groupedAsserts = rootClocks.zipWithIndex.groupBy(_._1).mapValues(values => values.map(_._2))
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// Step 5: Re-wire the top-level module
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val ports = collection.mutable.ArrayBuffer[Port]()
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val stmts = collection.mutable.ArrayBuffer[Statement]()
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val assertAnnos = collection.mutable.ArrayBuffer[Annotation]()
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// Step 5a: Connect all assertions to a single wire to match the order of our previous analysis
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val allAssertsWire = DefWire(NoInfo, "allAsserts", mInfo.assertUInt)
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val allAssertConnect = Connect(NoInfo, WRef(allAssertsWire), cat(mInfo.allAsserts.reverse))
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stmts ++= Seq(allAssertsWire, allAssertConnect)
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// Step 5b: Generate unique ports for each clock
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for ((clockRT, asserts) <- groupedAsserts) {
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val portName = namespace.newName(s"midasAsserts_${clockRT.ref}")
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val clockPortName = namespace.newName(s"midasAsserts_${clockRT.ref}_clock")
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val tpe = UIntType(IntWidth(asserts.size))
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val port = Port(NoInfo, portName, Output, tpe)
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val clockPort = Port(NoInfo, clockPortName, Output, ClockType)
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ports ++= Seq(port, clockPort)
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val bitExtracts = asserts.map(idx => DoPrim(PrimOps.Bits, Seq(WRef(allAssertsWire)), Seq(idx, idx), UIntType(IntWidth(1))))
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val connectAsserts = Connect(NoInfo, WRef(port), cat(bitExtracts.reverse))
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val connectClock = Connect(NoInfo, WRef(clockPort), WRef(clockRT.ref))
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stmts ++= Seq(connectClock, connectAsserts)
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// Generate the bridge Annotation
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val portRT = ModuleTarget(c.main, c.main).ref(portName)
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val clockPortRT = ModuleTarget(c.main, c.main).ref(clockPortName)
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val fcca = FAMEChannelConnectionAnnotation.source(portName, WireChannel, Some(clockPortRT), Seq(portRT))
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val assertMessages = asserts.map(formattedMessages(_))
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val bridgeAnno = BridgeIOAnnotation(
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target = portRT,
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widget = Some((p: Parameters) => new AssertBridgeModule(assertMessages)(p)),
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channelMapping = Map("" -> portName)
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)
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assertAnnos ++= Seq(fcca, bridgeAnno)
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}
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val wiredTopModule = topModule.copy(ports = topModule.ports ++ ports,
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body = Block(topModule.body +: stmts.toSeq))
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state.copy(
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circuit = c.copy(modules = wiredTopModule +: mods.filterNot(_.name == c.main)),
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form = HighForm,
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annotations = state.annotations ++ assertAnnos
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)
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}
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}
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def execute(state: CircuitState): CircuitState = {
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if (p(SynthAsserts)) synthesizeAsserts(state) else {
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// Still need to touch the file.
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val f = new FileWriter(new File(dir, s"${state.circuit.main}.asserts"))
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f.close
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state
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}
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if (p(SynthAsserts)) synthesizeAsserts(state) else state
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}
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}
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