hanchenye-llvm-project/llvm/test/CodeGen/AMDGPU
Max Kazantsev 69f6dfa0f8 [LICM] Use ICFLoopSafetyInfo in LICM
This patch makes LICM use `ICFLoopSafetyInfo` that is a smarter version
of LoopSafetyInfo that leverages power of Implicit Control Flow Tracking
to keep track of throwing instructions and give less pessimistic answers
to queries related to throws.

The ICFLoopSafetyInfo itself has been introduced in rL344601. This patch
enables it in LICM only.

Differential Revision: https://reviews.llvm.org/D50377
Reviewed By: apilipenko

llvm-svn: 346201
2018-11-06 02:44:49 +00:00
..
GlobalISel Revert "AMDGPU/GlobalISel: Implement select for G_INSERT" 2018-10-11 23:36:46 +00:00
32-bit-local-address-space.ll
InlineAsmCrash.ll
README
add-debug.ll
add.i16.ll
add.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
add.v2i16.ll
add_i1.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
add_i64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
add_i128.ll
addrspacecast-captured.ll
addrspacecast-constantexpr.ll
addrspacecast.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
adjust-writemask-invalid-copy.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
alignbit-pat.ll
alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
always-uniform.ll
amdgcn.bitcast.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
amdgcn.private-memory.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
amdgpu-alias-analysis.ll AMDGPU: Don't error on out of bounds address spaces 2018-09-11 04:00:41 +00:00
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-i16-to-i32.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-codegenprepare-idiv.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-inline.ll
amdgpu-shader-calling-convention.ll
amdgpu.private-memory.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
amdgpu.work-item-intrinsics.deprecated.ll
amdhsa-trap-num-sgprs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
amdpal-cs.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll
amdpal_scratch_mergedshader.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
and-gcn.ll
and.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
annotate-kernel-features-hsa-call.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
annotate-kernel-features-hsa.ll
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
atomic_cmp_swap_local.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
atomic_load_add.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_load_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomic_load_sub.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_buffer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_global_pointer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_local_pointer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_pixelshader.ll [AMDGPU] Fix the new atomic optimizer in pixel shaders. 2018-11-05 12:04:48 +00:00
atomic_optimizations_raw_buffer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_struct_buffer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_store_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomicrmw-nand.ll AMDGPU: Expand atomicrmw nand in IR 2018-10-02 03:50:56 +00:00
attr-amdgpu-flat-work-group-size.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
attr-amdgpu-num-sgpr-spill-to-smem.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
attr-amdgpu-num-sgpr.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
basic-call-return.ll
basic-loop.ll
bfe-combine.ll
bfe-patterns.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
bfe_uint.ll
bfi_int.ll AMDGPU: Scalarize vector argument types to calls 2018-07-31 19:05:14 +00:00
bfm.ll
big_alu.ll
bitcast-constant-to-vector.ll AMDGPU: Fix assertion with bitcast from i64 constant to v4i16 2018-11-02 02:43:55 +00:00
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
br_cc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll AMDGPU: Use scavengeRegisterBackwards 2018-10-30 01:33:14 +00:00
branch-relaxation.ll AMDGPU: Use scavengeRegisterBackwards 2018-10-30 01:33:14 +00:00
branch-uniformity.ll
break-smem-soft-clauses.mir
break-vmem-soft-clauses.mir
bswap.ll
buffer-schedule.ll
bug-vopc-commute.ll
build-vector-insert-elt-infloop.ll [LICM] Use ICFLoopSafetyInfo in LICM 2018-11-06 02:44:49 +00:00
build-vector-packed-partial-undef.ll AMDGPU: Fix packing undef parts of build_vector 2018-08-12 08:42:46 +00:00
build_vector.ll
byval-frame-setup.ll AMDGPU: Fix private handling for allowsMisalignedMemoryAccesses 2018-09-24 13:18:15 +00:00
call-argument-types.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
call-constexpr.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
call-encoding.ll
call-graph-register-usage.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
call-preserved-registers.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
call-return-types.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
call_fs.ll
callee-frame-setup.ll
callee-special-input-sgprs.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
callee-special-input-vgprs.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
calling-conventions.ll AMDGPU: Partially fix handling of packed amdgpu_ps arguments 2018-08-01 19:57:34 +00:00
captured-frame-index.ll
cayman-loop-bug.ll
cf-loop-on-constant.ll
cf-stack-bug.ll
cf_end.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes.ll AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
cgp-bitfield-extract.ll
clamp-modifier.ll AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
clamp-omod-special-case.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
clamp.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
cluster-flat-loads-postra.mir
cluster-flat-loads.mir
cndmask-no-def-vcc.ll
coalescer-extend-pruned-subrange.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-identical-values-undef.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-subranges-another-copymi-not-live.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-subranges-another-prune-error.mir AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
coalescer-subreg-join.mir AMDGPU: Turn D16 for MIMG instructions into a regular operand 2018-06-21 13:36:01 +00:00
coalescer-subregjoin-fullcopy.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-with-subregs-bad-identical.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer_distribute.ll AMDGPU: Don't use spir_kernel in a test 2018-07-05 17:01:29 +00:00
coalescer_remat.ll
coalescing-with-subregs-in-loop-bug.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
code-object-v3.ll AMDGPU: Rename isAmdCodeObjectV2 -> isAmdHsaOrMesa 2018-10-04 21:02:16 +00:00
codegen-prepare-addrmode-sext.ll
collapse-endcf.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
combine_vloads.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
comdat.ll
commute-compares.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
commute-shifts.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
commute_modifiers.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
complex-folding.ll
concat_vectors.ll DAG: Fix creating concat_vectors with illegal type 2018-06-15 12:09:15 +00:00
constant-address-space-32bit.ll AMDGPU: Handle 32-bit address wraparounds for SMRD opcodes 2018-08-29 20:03:00 +00:00
constant-fold-imm-immreg.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
control-flow-optnone.ll
convergent-inlineasm.ll
copy-illegal-type.ll [DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target. 2018-08-28 03:47:20 +00:00
copy-to-reg.ll
couldnt-join-subrange-3.mir AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
cross-block-use-is-not-abi-copy.ll DAG: Don't use ABI copies in some contexts 2018-08-30 05:49:28 +00:00
ctlz.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
ctlz_zero_undef.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop64.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
cttz_zero_undef.ll
cube.ll
cvt_f32_ubyte.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence.ll AMDGPU: Fix DAG divergence not reporting flat loads 2018-09-04 18:58:19 +00:00
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
dagcombine-setcc-select.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dead_copy.mir
debug-value.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
debug-value2.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
debug.ll
debugger-emit-prologue.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
debugger-insert-nops.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
default-fp-mode.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
detect-dead-lanes.mir
directive-amdgcn-target.ll AMDGPU: Add sram-ecc feature 2018-11-05 22:44:19 +00:00
disconnected-predset-break-bug.ll
div_i128.ll AMDGPU: Error more gracefully on libcalls 2018-08-08 16:58:39 +00:00
diverge-extra-formal-args.ll
diverge-interp-mov-lower.ll
diverge-switch-default.ll [AMDGPU] restore r342722 which was reverted with r342743 2018-09-25 09:39:21 +00:00
divrem24-assume.ll [AMDGPU] Use AssumptionCacheTracker in the divrem32 expansion 2018-07-25 17:02:11 +00:00
drop-mem-operand-move-smrd.ll
ds-combine-large-stride.ll
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll
ds_read2.ll
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2st64.ll
ds_write2.ll
ds_write2st64.ll
dynamic_stackalloc.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
early-if-convert-cost.ll
early-if-convert.ll
early-inline-alias.ll
early-inline.ll Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
elf-header-flags-mach.ll AMDGPU: Add sram-ecc feature 2018-11-05 22:44:19 +00:00
elf-header-flags-sram-ecc.ll AMDGPU: Add sram-ecc feature 2018-11-05 22:44:19 +00:00
elf-header-flags-xnack.ll
elf-header-osabi.ll
elf-notes.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
elf.ll
elf.r600.ll
else.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir AMDGPU: Don't delete instructions if S_ENDPGM has implicit uses 2018-08-28 18:55:55 +00:00
enqueue-kernel.ll
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extload-private.ll
extload.ll
extract-lowbits.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
extract-subvector-equal-length.ll [CodeGen] Fix assert in SelectionDAG::computeKnownBits 2018-08-13 18:44:21 +00:00
extract-vector-elt-build-vector-combine.ll
extract_vector_elt-f16.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-f64.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
extract_vector_elt-i16.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-i64.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extractelt-to-trunc.ll
fabs.f16.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fabs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fadd-fma-fmul-combine.ll
fadd.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fadd.ll Utilize new SDNode flag functionality to expand current support for fadd 2018-06-18 23:44:59 +00:00
fadd64.ll
fcanonicalize-elimination.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fcanonicalize.f16.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
fcanonicalize.ll AMDGPU: Expand vector canonicalizes 2018-09-18 01:51:33 +00:00
fceil.ll
fceil64.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fcmp.ll
fcmp64.ll
fconst64.ll
fcopysign.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f32.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fdiv.f16.ll Utilize new SDNode flag functionality to expand current support for fdiv 2018-06-15 20:44:55 +00:00
fdiv.f64.ll
fdiv.ll
fdiv32-to-rcp-folding.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
fdot2.ll [AMDGPU] [AMDGPU] Support a fdot2 pattern. 2018-07-16 18:19:59 +00:00
fence-barrier.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ffloor.f64.ll
ffloor.ll
fix-vgpr-copies.mir
fix-wwm-liveness.mir [AMDGPU] Reworked SIFixWWMLiveness 2018-08-02 23:31:32 +00:00
flat-address-space.ll
flat-for-global-subtarget-feature.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
flat-load-clustering.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
flat-scratch-reg.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
flat_atomics.ll
flat_atomics_i64.ll
floor.ll
fma-combine.ll
fma.f64.ll
fma.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmad.ll
fmax.ll
fmax3.f64.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax3.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax_legacy.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax_legacy.f64.ll AMDGPU: Cleanup min/max legacy tests 2018-08-12 19:29:53 +00:00
fmax_legacy.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmaxnum.f64.ll
fmaxnum.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmaxnum.r600.ll AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests 2018-07-31 20:38:42 +00:00
fmed3.ll AMDGPU: Don't form fmed3 if it will require materialization 2018-09-18 02:34:54 +00:00
fmin.ll
fmin3.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmin_fmax_legacy.amdgcn.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmin_legacy.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmin_legacy.f64.ll AMDGPU: Cleanup min/max legacy tests 2018-08-12 19:29:53 +00:00
fmin_legacy.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.f64.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.r600.ll AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests 2018-07-31 20:38:42 +00:00
fmul-2-combine-multi-use.ll DAG: Enhance isKnownNeverNaN 2018-08-03 18:27:52 +00:00
fmul.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmul.ll
fmul64.ll
fmuladd.f16.ll
fmuladd.f32.ll
fmuladd.f64.ll
fmuladd.v2f16.ll
fnearbyint.ll
fneg-combines.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fneg-combines.si.ll AMDGPU: Address todo for handling 1/(2 pi) 2018-08-15 21:03:55 +00:00
fneg-fabs.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg-fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg-fabs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg.f16.ll
fneg.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg.ll
fold-cndmask.mir
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir [AMDGPU] Preliminary patch for divergence driven instruction selection. Operands Folding 1. 2018-08-30 13:55:04 +00:00
fold-imm-f16-f32.mir
fold-immediate-operand-shrink-with-carry.mir MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
fold-immediate-operand-shrink.mir Don't count debug instructions towards neighborhood count 2018-08-30 07:18:19 +00:00
fold-immediate-output-mods.mir
fold-implicit-operand.mir
fold-multiple.mir
fold-operands-order.mir
fold-vgpr-copy.mir [AMDGPU] Fold copy (copy vgpr) 2018-09-27 18:55:20 +00:00
force-alwaysinline-lds-global-address-codegen.ll AMDGPU: Always run AMDGPUAlwaysInline 2018-10-03 02:47:25 +00:00
force-alwaysinline-lds-global-address.ll AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
fp-classify.ll AMDGPU: Combine and of seto/setuo and fp_class 2018-08-10 18:58:56 +00:00
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fp_to_uint.f64.ll
fp_to_uint.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fpext-free.ll
fpext.f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fpext.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-elimination.ll [CodeGen] Emit more precise AssertZext/AssertSext nodes. 2018-07-11 23:26:35 +00:00
frem.ll
fsqrt.f64.ll
fsqrt.ll
fsub.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fsub.ll
fsub64.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
function-returns.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
gep-address-space.ll
gfx902-without-xnack.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
global-constant.ll
global-directive.ll
global-extload-i16.ll
global-smrd-unknown.ll
global-variable-relocs.ll
global_atomics.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
global_atomics_i64.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
global_smrd.ll AMDGPU: Use GOT PSV since it has an address space now 2018-09-10 02:23:39 +00:00
global_smrd_cfg.ll
gv-const-addrspace.ll
gv-offset-folding.ll
half.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
hazard-buffer-store-v-interp.mir [AMDGPU] Add VALU to V_INTERP Instructions 2018-07-05 12:02:07 +00:00
hazard-inlineasm.mir
hazard.mir [AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting 2018-09-10 10:14:48 +00:00
hoist-cond.ll
hsa-default-device.ll
hsa-fp-mode.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa-func-align.ll
hsa-func.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa-globals.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg.ll
hsa-metadata-enqueue-kernel.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa-metadata-from-llvm-ir-full.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa-metadata-hidden-args.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa-metadata-images.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa-metadata-invalid-ocl-version-1.ll
hsa-metadata-invalid-ocl-version-2.ll
hsa-metadata-invalid-ocl-version-3.ll
hsa-metadata-kernel-code-props.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa-metadata-kernel-debug-props.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa-note-no-func.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
hsa.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
huge-private-buffer.ll
i1-copy-from-loop.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
i1-copy-phi.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
i8-to-double-to-float.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
icmp64.ll
idiv-licm.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
idot2.ll AMDGPU: Actually commit re-run of update_llc_test_checks 2018-08-31 15:05:06 +00:00
idot4.ll [AMDGPU] Match signed dot4/8 pattern. 2018-10-04 16:57:37 +00:00
idot8.ll [AMDGPU] Handle the idot8 pattern generated by FE. 2018-11-01 22:48:19 +00:00
illegal-sgpr-to-vgpr-copy.ll
image-attributes.ll
image-resource-id.ll
image-schedule.ll AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
imm.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
imm16.ll
immv216.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
indirect-addressing-si-noopt.ll
indirect-addressing-si.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
indirect-private-64.ll
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
inline-asm.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
inline-attr.ll
inline-calls.ll
inline-constraints.ll
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll
input-mods.ll
insert-skips-kill-uncond.mir AMDGPU: Add implicit def of SCC to kill and indirect pseudos 2018-06-21 13:36:08 +00:00
insert-waitcnts-callee.mir
insert-waitcnts-exp.mir
insert_subreg.ll
insert_vector_elt.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
insert_vector_elt.v2i16.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
inserted-wait-states.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
internalize.ll AMDGPU: Stop forcing internalize at -O0 2018-08-31 06:02:36 +00:00
invalid-addrspacecast.ll AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bit 2018-09-10 11:59:27 +00:00
invalid-alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
ipra.ll
jump-address.ll
kcache-fold.ll
kernarg-stack-alignment.ll
kernel-args.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
kernel-argument-dag-lowering.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
known-never-nan.ll DAG: Handle extract_vector_elt in isKnownNeverNaN 2018-09-03 14:01:03 +00:00
known-never-snan.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
knownbits-recursion.ll
large-alloca-compute.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
large-alloca-graphics.ll
large-constant-initializer.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
large-work-group-promote-alloca.ll
lds-alignment.ll
lds-bounds.ll AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI 2018-10-17 15:37:48 +00:00
lds-global-non-entry-func.ll
lds-initializer.ll
lds-m0-init-in-loop.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
lds-zero-initializer.ll
lds_atomic_f32.ll
legalize-fp-load-invariant.ll [AMDGPU] Rename pass "isel" to "amdgpu-isel" 2018-10-03 03:38:22 +00:00
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
lit.local.cfg
literals.ll
liveness.mir
llvm.AMDGPU.kill.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
llvm.SI.load.dword.ll
llvm.SI.tbuffer.store.ll
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll
llvm.amdgcn.atomic.inc.ll
llvm.amdgcn.buffer.atomic.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
llvm.amdgcn.buffer.store.format.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.buffer.store.format.ll
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.class.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pk.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pkrtz.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
llvm.amdgcn.div.fixup.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.div.fixup.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.fmas.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
llvm.amdgcn.div.scale.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll AMDGPU: Force skip over s_sendmsg and exp instructions 2018-07-30 09:23:59 +00:00
llvm.amdgcn.fcmp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.fmad.ftz.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmad.ftz.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16 2018-08-15 21:25:20 +00:00
llvm.amdgcn.image.a16.dim.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.atomic.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.d16.dim.ll
llvm.amdgcn.image.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll [AMDGPU] Add support for a16 modifiear for gfx9 2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll
llvm.amdgcn.image.gather4.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.gather4.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.getlod.dim.ll AMDGPU: Select MIMG instructions manually in SITargetLowering 2018-06-21 13:36:57 +00:00
llvm.amdgcn.image.load.a16.d16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.load.a16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Add support for a16 modifiear for gfx9 2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.sample.d16.dim.ll
llvm.amdgcn.image.sample.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.sample.ltolz.ll [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero 2018-08-01 12:12:01 +00:00
llvm.amdgcn.image.sample.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.store.a16.d16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.store.a16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll [AMDGPU] Avoid using divergent value in mubuf addr64 descriptor 2018-08-02 22:53:57 +00:00
llvm.amdgcn.init.exec.ll
llvm.amdgcn.interp.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
llvm.amdgcn.kill.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
llvm.amdgcn.mov.dpp.ll run post-RA hazard recognizer pass late 2018-07-16 10:02:41 +00:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.ps.live.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
llvm.amdgcn.raw.buffer.atomic.ll AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics 2018-10-08 16:53:48 +00:00
llvm.amdgcn.raw.buffer.load.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.ll [AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics 2018-10-03 10:29:43 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.ll [AMDGPU] Allow int types for MUBUF vdata 2018-08-21 11:08:12 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.load.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.store.d16.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.store.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.sad.hi.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.sdot4.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.sdot8.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.sendmsg.ll AMDGPU: Force skip over s_sendmsg and exp instructions 2018-07-30 09:23:59 +00:00
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.struct.buffer.atomic.ll AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics 2018-10-08 16:53:48 +00:00
llvm.amdgcn.struct.buffer.load.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.ll [AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics 2018-10-03 10:29:43 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.ll [AMDGPU] Allow int types for MUBUF vdata 2018-08-21 11:08:12 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.load.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.store.d16.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.store.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.tbuffer.store.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.udot4.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.udot8.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.workgroup.id.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
llvm.amdgcn.workitem.id.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
llvm.amdgcn.wqm.vote.ll
llvm.amdgcn.writelane.ll AMDGPU: Fix getInstSizeInBytes 2018-08-29 07:46:09 +00:00
llvm.ceil.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.cos.f16.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.cos.ll
llvm.dbg.value.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.exp2.f16.ll
llvm.exp2.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
llvm.floor.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.fma.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.fmuladd.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log2.f16.ll
llvm.log2.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
llvm.log10.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log10.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.maxnum.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
llvm.memcpy.ll
llvm.minnum.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.sin.f16.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.sin.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.sqrt.f16.ll
llvm.trunc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-constant-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-constant-i16.ll
load-constant-i32.ll [AMDGPU] Split v32i32 loads 2018-08-31 22:43:36 +00:00
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-global-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-global-i16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-global-i32.ll [AMDGPU] Split v32i32 loads 2018-08-31 22:43:36 +00:00
load-global-i64.ll
load-hi16.ll
load-input-fold.ll
load-lo16.ll
load-local-f32-no-ds128.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-local-i8.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-local-i16.ll [SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes 2018-10-30 10:32:11 +00:00
load-local-i32.ll [AMDGPU] Split v32i32 loads 2018-08-31 22:43:36 +00:00
load-local-i64.ll
load-select-ptr.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-weird-sizes.ll
local-64.ll
local-atomics.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
local-atomics64.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
local-memory.amdgcn.ll
local-memory.ll
local-memory.r600.ll
local-stack-slot-offset.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
loop-address.ll
loop-idiom.ll
loop_break.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
loop_exit_with_xor.ll
lower-kernargs.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
lower-mem-intrinsics.ll
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll
lshr.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
macro-fusion-cluster-vcc-uses.mir
mad-combine.ll
mad-mix-hi.ll AMDGPU: Remove custom BUILD_VECTOR combine 2018-10-30 01:37:59 +00:00
mad-mix-lo.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
mad-mix.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll AMDGPU: Remove broken i16 ternary patterns 2018-08-07 21:54:37 +00:00
madak-inline-constant.mir [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32. 2018-09-10 16:42:49 +00:00
madak.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
madmk.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
max-literals.ll
max.i16.ll
max.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
max3.ll
mem-builtins.ll
memory-legalizer-atomic-cmpxchg.ll
memory-legalizer-atomic-fence.ll
memory-legalizer-atomic-insert-end.mir AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
memory-legalizer-atomic-rmw.ll
memory-legalizer-invalid-addrspace.mir
memory-legalizer-invalid-syncscope.ll
memory-legalizer-load.ll
memory-legalizer-local.mir
memory-legalizer-multiple-mem-operands-atomics.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
memory-legalizer-region.mir
memory-legalizer-store-infinite-loop.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
memory-legalizer-store.ll
memory_clause.ll run post-RA hazard recognizer pass late 2018-07-16 10:02:41 +00:00
memory_clause.mir AMDGPU: Turn D16 for MIMG instructions into a regular operand 2018-06-21 13:36:01 +00:00
merge-load-store-physreg.mir
merge-load-store-vreg.mir [AMDGPU] Fix ds combine with subregs 2018-09-25 23:33:18 +00:00
merge-load-store.mir
merge-m0.mir
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
mesa_regression.ll
min.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
min3.ll
misched-killflags.mir [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
missing-store.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
move-addr64-rsrc-dead-subreg-writes.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-legalize-operands.ll [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions 2018-10-08 18:47:01 +00:00
mubuf-legalize-operands.mir [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions 2018-10-08 18:47:01 +00:00
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
mul.i16.ll AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on calls 2018-07-31 19:17:47 +00:00
mul.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
mul_int24.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul_uint24-amdgcn.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul_uint24-r600.ll
multi-divergent-exit-region.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
multilevel-break.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
nested-calls.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
nested-loop-conditions.ll AMDGPU: Remove PHI loop condition optimization 2018-10-31 13:26:48 +00:00
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-shrink-extloads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
noop-shader-O0.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
nop-data.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
not-scalarize-volatile-load.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
nullptr.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
omod-nsz-flag.mir AMDGPU: Check NSZ MI flag when folding omod 2018-08-12 08:44:25 +00:00
omod.ll
opencl-image-metadata.ll
operand-folding.ll
operand-spacing.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
opt-sgpr-to-vgpr-copy.mir
optimize-if-exec-masking.mir AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
or.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
over-max-lds-size.ll
pack.v2f16.ll
pack.v2i16.ll
packed-op-sel.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
perfhint.ll
permute.ll
phi-elimination-assertion.mir [PHIElimination] Lower a PHI node with only undef uses as IMPLICIT_DEF 2018-09-30 17:26:58 +00:00
pk_max_f16_literal.ll
postra-norename.mir
predicate-dp4.ll
predicates.ll
print-mir-custom-pseudo.ll [AMDGPU] Rename pass "isel" to "amdgpu-isel" 2018-10-03 03:38:22 +00:00
private-access-no-objects.ll
private-element-size.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
promote-alloca-calling-conv.ll
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
promote-alloca-padding-size-estimate.ll Revert r345542: AMDGPU: Enable code object v3 by default 2018-10-30 22:02:40 +00:00
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-volatile.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll AMDGPU: Fix r600 test 2018-09-11 04:39:16 +00:00
r600.bitcast.ll
r600.extract-lowbits.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.work-item-intrinsics.ll AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS 2018-08-01 18:36:07 +00:00
r600cfg.ll
rcp-pattern.ll
rcp_iflag.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
read_register.ll
readcyclecounter.ll
readlane_exec0.mir
reduce-build-vec-ext-to-ext-build-vec.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
reduction.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
reg-coalescer-sched-crash.ll
regcoal-subrange-join-seg.mir Shrink interval after moving copy in removePartialRedundancy 2018-06-18 17:16:39 +00:00
regcoal-subrange-join.mir
regcoalesce-dbg.mir MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
regcoalesce-prune.mir
regcoalescing-remove-partial-redundancy-assert.mir [RegisterCoalescer] Fix for assert in removePartialRedundancy 2018-08-23 17:28:33 +00:00
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir RenameIndependentSubregs: Fix handling of undef tied operands 2018-07-09 20:07:03 +00:00
reorder-stores.ll
reqd-work-group-size.ll
ret.ll AMDGPU: Fix code size for return_to_epilog pseudo 2018-07-27 09:15:03 +00:00
ret_jump.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_addk_i32.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
saddo.ll
salu-to-valu.ll
sampler-resource-id.ll
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir
scalar_to_vector.ll AMDGPU: Fix scalar_to_vector for v4i16/v4f16 2018-06-20 19:45:48 +00:00
sched-crash-dbg-value.mir MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit.ll
schedule-regpressure-limit2.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit3.ll
schedule-regpressure.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
schedule-vs-if-nested-loop-failure.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
schedule-vs-if-nested-loop.ll
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
sdiv.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
sdivrem24.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
sdivrem64.ll
sdwa-gfx9.mir
sdwa-peephole-instr.mir
sdwa-peephole.ll
sdwa-preserve.mir
sdwa-scalar-ops.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
sdwa-vop2-64bit.mir
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
select-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
select-opt.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
select-vectors.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
select.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
select.ll
select64.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir
set-dx10.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll Check shouldReduceLoadWidth from SimplifySetCC 2018-10-31 21:24:30 +00:00
setcc-opt.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
setcc-sext.ll
setcc.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
setcc64.ll
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
sgpr-control-flow.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
sgpr-spill-wrong-stack-id.mir StackSlotColoring: Decide colors per stack ID 2018-06-25 16:05:55 +00:00
sgprcopies.ll
shader-addr64-nonuniform.ll [AMDGPU] Avoid using divergent value in mubuf addr64 descriptor 2018-08-02 22:53:57 +00:00
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shift-i128.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
shl-add-to-add-shl.ll
shl.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
shl.v2i16.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
shl_add_constant.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
shl_add_ptr.ll
shrink-add-sub-constant.ll
shrink-carry.mir
shrink-vop3-carry-out.mir
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
si-annotate-cfg-loop-assert.ll
si-fix-sgpr-copies.mir
si-instr-info-correct-implicit-operands.ll
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
si-scheduler.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
si-sgpr-spill.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
si-spill-cf.ll
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll
si-vector-hang.ll
sibling-call.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
sign_extend.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
simplify-libcalls.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
simplifydemandedbits-recursion.ll
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll [AMDGPU] Add instruction selection for i1 to f16 conversion 2018-09-19 16:32:12 +00:00
skip-if-dead.ll AMDGPU: Force skip over s_sendmsg and exp instructions 2018-07-30 09:23:59 +00:00
smed3.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
sminmax.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
sminmax.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
smrd-fold-offset.mir AMDGPU: Divergence-driven selection of scalar buffer load intrinsics 2018-10-17 15:37:30 +00:00
smrd-vccz-bug.ll
smrd.ll StructurizeCFG: Simplify inserted PHI nodes 2018-10-17 15:37:41 +00:00
sopk-compares.ll
spill-alloc-sgpr-init-bug.ll
spill-before-exec.mir [RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled 2018-09-25 18:37:38 +00:00
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll
spill-empty-live-interval.mir
spill-m0.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
spill-offset-calculation.ll [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits 2018-07-26 19:47:51 +00:00
spill-scavenge-offset.ll
spill-to-smem-m0.ll
spill-wide-sgpr.ll Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
split-scalar-i64-add.ll CodeGen: Make computeRegisterLiveness consider successors 2018-08-30 07:17:51 +00:00
split-smrd.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
split-vector-memoperand-offsets.ll
splitkit.mir
sra.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
srem.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
srl.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
ssubo.ll
stack-realign.ll
stack-size-overflow.ll
stack-slot-color-sgpr-vgpr-spills.mir
store-barrier.ll
store-global.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
store-hi16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
store-local.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
store-private.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
store-v3i64.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
store-vector-ptrs.ll
store-weird-sizes.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
store_typed.ll
stress-calls.ll Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
structurize.ll
structurize1.ll
sub.i16.ll
sub.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
sub.v2i16.ll [AMDGPU] Remove useless check from test. NFC. 2018-09-25 01:24:54 +00:00
sub_i1.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
subreg-coalescer-crash.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
subreg-coalescer-undef-use.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
subreg_interference.mir
swizzle-export.ll
syncscopes.ll
tail-call-cgp.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
trunc-combine.ll AMDGPU: Fix assert in truncate combine with vectors 2018-07-12 19:40:16 +00:00
trunc-store-f64-to-f16.ll
trunc-store-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
trunc-store.ll
trunc-vector-store-assertion-failure.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
trunc.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
tti-unroll-prefs.ll
twoaddr-mad.mir
uaddo.ll
udiv.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
udivrem.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
udivrem24.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
udivrem64.ll
uint_to_fp.f64.ll
uint_to_fp.i64.ll
uint_to_fp.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
uitofp.f16.ll [AMDGPU] Add instruction selection for i1 to f16 conversion 2018-09-19 16:32:12 +00:00
umed3.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
unaligned-load-store.ll DAG: Fix expansion of unaligned FP loads and stores 2018-09-13 12:14:23 +00:00
undefined-physreg-sgpr-spill.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
undefined-subreg-liverange.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
uniform-crash.ll
uniform-loop-inside-nonuniform.ll
unify-metadata.ll
unigine-liveness-crash.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
unknown-processor.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
unpack-half.ll
unroll.ll
unsupported-calls.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
unsupported-cc.ll
urem.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
use-sgpr-multiple-times.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
usubo.ll
v1i64-kernel-arg.ll
v_cndmask.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
v_cvt_pk_u8_f32.ll
v_mac.ll
v_mac_f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
v_madak_f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
v_swap_b32.mir [AMDGPU] Match v_swap_b32 2018-10-29 17:26:01 +00:00
valu-i1.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
vccz-corrupt-bug-workaround.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
vector-alloca-addrspacecast.ll
vector-alloca-atomic.ll
vector-alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
vector-extract-insert.ll
vector-legalizer-divergence.ll
vectorize-global-local.ll
verifier-implicit-virtreg-invalid-physreg-liveness.mir MachineVerifier: Fix assert on implicit virtreg use 2018-08-27 17:40:09 +00:00
vertex-fetch-encoding.ll
vgpr-spill-emergency-stack-slot-compute.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
vgpr-spill-emergency-stack-slot.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
vi-removed-intrinsics.ll
vop-shrink-frame-index.mir
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect.ll
vselect64.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
waitcnt-back-edge-loop.mir
waitcnt-debug.mir
waitcnt-flat.ll
waitcnt-loop-single-basic-block.mir
waitcnt-looptest.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
waitcnt-no-redundant.mir
waitcnt-permute.mir
waitcnt.mir
wave_dispatch_regs.ll
widen-smrd-loads.ll
widen-vselect-and-mask.ll
widen_extending_scalar_loads.ll
wqm.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
wqm.mir
write-register-vgpr-into-sgpr.ll
write_register.ll
wrong-transalu-pos-fix.ll
xfail.r600.bitcast.ll
xnor.ll
xor.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
zero_extend.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
zext-i64-bit-operand.ll
zext-lid.ll [SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt 2018-10-31 19:57:36 +00:00

README

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.