AMDGPU: Cleanup min/max legacy tests
Also add some more tests in preparation for a future patch. llvm-svn: 339526
This commit is contained in:
Matt Arsenault
parent
1201301b94
commit
3763f307bd
|
|
@ -1,10 +1,48 @@
|
|||
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
|
||||
|
||||
; Make sure we don't try to form FMAX_LEGACY nodes with f64
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_uge_f64
|
||||
define amdgpu_kernel void @test_fmax_legacy_uge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmax_legacy_uge_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmax_legacy_uge_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
|
@ -18,8 +56,45 @@ define amdgpu_kernel void @test_fmax_legacy_uge_f64(double addrspace(1)* %out, d
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_oge_f64
|
||||
define amdgpu_kernel void @test_fmax_legacy_oge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmax_legacy_oge_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmax_legacy_oge_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
|
@ -33,8 +108,45 @@ define amdgpu_kernel void @test_fmax_legacy_oge_f64(double addrspace(1)* %out, d
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_ugt_f64
|
||||
define amdgpu_kernel void @test_fmax_legacy_ugt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmax_legacy_ugt_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmax_legacy_ugt_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
|
@ -48,8 +160,45 @@ define amdgpu_kernel void @test_fmax_legacy_ugt_f64(double addrspace(1)* %out, d
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_ogt_f64
|
||||
define amdgpu_kernel void @test_fmax_legacy_ogt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmax_legacy_ogt_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmax_legacy_ogt_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
|
@ -63,5 +212,7 @@ define amdgpu_kernel void @test_fmax_legacy_ogt_f64(double addrspace(1)* %out, d
|
|||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s
|
||||
; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GCN-SAFE -check-prefix=FUNC %s
|
||||
; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN-NONAN -check-prefix=GCN -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() #1
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_uge_f32
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
|
||||
; EG: MAX
|
||||
define amdgpu_kernel void @test_fmax_legacy_uge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
|
|
@ -25,11 +25,37 @@ define amdgpu_kernel void @test_fmax_legacy_uge_f32(float addrspace(1)* %out, fl
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_oge_f32
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32_nnan_src:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-DAG: v_add_f32_e32 [[ADD_A:v[0-9]+]], 1.0, [[A]]
|
||||
; GCN-DAG: v_add_f32_e32 [[ADD_B:v[0-9]+]], 2.0, [[B]]
|
||||
|
||||
; GCN-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
|
||||
; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
|
||||
|
||||
; EG: MAX
|
||||
define amdgpu_kernel void @test_fmax_legacy_uge_f32_nnan_src(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
||||
|
||||
%a = load volatile float, float addrspace(1)* %gep.0, align 4
|
||||
%b = load volatile float, float addrspace(1)* %gep.1, align 4
|
||||
%a.nnan = fadd nnan float %a, 1.0
|
||||
%b.nnan = fadd nnan float %b, 2.0
|
||||
|
||||
%cmp = fcmp uge float %a.nnan, %b.nnan
|
||||
%val = select i1 %cmp, float %a.nnan, float %b.nnan
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_fmax_legacy_oge_f32:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; EG: MAX
|
||||
define amdgpu_kernel void @test_fmax_legacy_oge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -45,11 +71,11 @@ define amdgpu_kernel void @test_fmax_legacy_oge_f32(float addrspace(1)* %out, fl
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_ugt_f32
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; FUNC-LABEL: {{^}}test_fmax_legacy_ugt_f32:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; EG: MAX
|
||||
define amdgpu_kernel void @test_fmax_legacy_ugt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -65,11 +91,11 @@ define amdgpu_kernel void @test_fmax_legacy_ugt_f32(float addrspace(1)* %out, fl
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_ogt_f32
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; EG: MAX
|
||||
define amdgpu_kernel void @test_fmax_legacy_ogt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -86,10 +112,10 @@ define amdgpu_kernel void @test_fmax_legacy_ogt_f32(float addrspace(1)* %out, fl
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v1f32:
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; EG: MAX
|
||||
define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(<1 x float> addrspace(1)* %out, <1 x float> addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -106,12 +132,12 @@ define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(<1 x float> addrspace(1)*
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32:
|
||||
; SI-SAFE: v_max_legacy_f32_e32
|
||||
; SI-SAFE: v_max_legacy_f32_e32
|
||||
; SI-SAFE: v_max_legacy_f32_e32
|
||||
; SI-NONAN: v_max_f32_e32
|
||||
; SI-NONAN: v_max_f32_e32
|
||||
; SI-NONAN: v_max_f32_e32
|
||||
; GCN-SAFE: v_max_legacy_f32_e32
|
||||
; GCN-SAFE: v_max_legacy_f32_e32
|
||||
; GCN-SAFE: v_max_legacy_f32_e32
|
||||
; GCN-NONAN: v_max_f32_e32
|
||||
; GCN-NONAN: v_max_f32_e32
|
||||
; GCN-NONAN: v_max_f32_e32
|
||||
define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr <3 x float>, <3 x float> addrspace(1)* %in, i32 %tid
|
||||
|
|
@ -126,13 +152,13 @@ define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32(<3 x float> addrspace(1)*
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmax_legacy_ogt_f32_multi_use
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-NOT: v_max_
|
||||
; SI: v_cmp_gt_f32
|
||||
; SI-NEXT: v_cndmask_b32
|
||||
; SI-NOT: v_max_
|
||||
; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32_multi_use:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-NOT: v_max_
|
||||
; GCN: v_cmp_gt_f32
|
||||
; GCN-NEXT: v_cndmask_b32
|
||||
; GCN-NOT: v_max_
|
||||
|
||||
; EG: MAX
|
||||
define amdgpu_kernel void @test_fmax_legacy_ogt_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
|
||||
|
|
|
|||
|
|
@ -1,20 +1,150 @@
|
|||
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
define amdgpu_kernel void @test_fmin_legacy_uge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmin_legacy_uge_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmin_legacy_uge_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_f64
|
||||
define amdgpu_kernel void @test_fmin_legacy_f64(<4 x double> addrspace(1)* %out, <4 x double> inreg %reg0) #0 {
|
||||
%r0 = extractelement <4 x double> %reg0, i32 0
|
||||
%r1 = extractelement <4 x double> %reg0, i32 1
|
||||
%r2 = fcmp uge double %r0, %r1
|
||||
%r3 = select i1 %r2, double %r1, double %r0
|
||||
%vec = insertelement <4 x double> undef, double %r3, i32 0
|
||||
store <4 x double> %vec, <4 x double> addrspace(1)* %out, align 16
|
||||
ret void
|
||||
%a = load double, double addrspace(1)* %gep.0, align 8
|
||||
%b = load double, double addrspace(1)* %gep.1, align 8
|
||||
|
||||
%cmp = fcmp uge double %a, %b
|
||||
%val = select i1 %cmp, double %b, double %a
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @test_fmin_legacy_ugt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmin_legacy_ugt_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmin_legacy_ugt_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
||||
%a = load double, double addrspace(1)* %gep.0, align 8
|
||||
%b = load double, double addrspace(1)* %gep.1, align 8
|
||||
|
||||
%cmp = fcmp ugt double %a, %b
|
||||
%val = select i1 %cmp, double %b, double %a
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_ule_f64
|
||||
define amdgpu_kernel void @test_fmin_legacy_ule_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmin_legacy_ule_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmin_legacy_ule_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
|
@ -28,38 +158,45 @@ define amdgpu_kernel void @test_fmin_legacy_ule_f64(double addrspace(1)* %out, d
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_ole_f64
|
||||
define amdgpu_kernel void @test_fmin_legacy_ole_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
||||
%a = load double, double addrspace(1)* %gep.0, align 8
|
||||
%b = load double, double addrspace(1)* %gep.1, align 8
|
||||
|
||||
%cmp = fcmp ole double %a, %b
|
||||
%val = select i1 %cmp, double %a, double %b
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_olt_f64
|
||||
define amdgpu_kernel void @test_fmin_legacy_olt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
||||
%a = load double, double addrspace(1)* %gep.0, align 8
|
||||
%b = load double, double addrspace(1)* %gep.1, align 8
|
||||
|
||||
%cmp = fcmp olt double %a, %b
|
||||
%val = select i1 %cmp, double %a, double %b
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_ult_f64
|
||||
define amdgpu_kernel void @test_fmin_legacy_ult_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmin_legacy_ult_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_nge_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmin_legacy_ult_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_nge_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
|
@ -73,5 +210,215 @@ define amdgpu_kernel void @test_fmin_legacy_ult_f64(double addrspace(1)* %out, d
|
|||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @test_fmin_legacy_oge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmin_legacy_oge_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmin_legacy_oge_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
||||
%a = load double, double addrspace(1)* %gep.0, align 8
|
||||
%b = load double, double addrspace(1)* %gep.1, align 8
|
||||
|
||||
%cmp = fcmp oge double %a, %b
|
||||
%val = select i1 %cmp, double %b, double %a
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @test_fmin_legacy_ogt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmin_legacy_ogt_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmin_legacy_ogt_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
||||
%a = load double, double addrspace(1)* %gep.0, align 8
|
||||
%b = load double, double addrspace(1)* %gep.1, align 8
|
||||
|
||||
%cmp = fcmp ogt double %a, %b
|
||||
%val = select i1 %cmp, double %b, double %a
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @test_fmin_legacy_ole_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmin_legacy_ole_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_le_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmin_legacy_ole_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_le_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
||||
%a = load double, double addrspace(1)* %gep.0, align 8
|
||||
%b = load double, double addrspace(1)* %gep.1, align 8
|
||||
|
||||
%cmp = fcmp ole double %a, %b
|
||||
%val = select i1 %cmp, double %a, double %b
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @test_fmin_legacy_olt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
; SI-LABEL: test_fmin_legacy_olt_f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s10, 0
|
||||
; SI-NEXT: s_mov_b32 s11, s7
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_mov_b32 s4, s0
|
||||
; SI-NEXT: s_mov_b32 s5, s1
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_fmin_legacy_olt_f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s3
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s1
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
|
||||
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
||||
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
||||
|
||||
%a = load double, double addrspace(1)* %gep.0, align 8
|
||||
%b = load double, double addrspace(1)* %gep.1, align 8
|
||||
|
||||
%cmp = fcmp olt double %a, %b
|
||||
%val = select i1 %cmp, double %a, double %b
|
||||
store double %val, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=FUNC %s
|
||||
; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN-NONAN -check-prefix=GCN -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() #1
|
||||
|
||||
|
|
@ -10,25 +10,24 @@ declare i32 @llvm.r600.read.tidig.x() #1
|
|||
|
||||
; FUNC-LABEL: {{^}}s_test_fmin_legacy_subreg_inputs_f32:
|
||||
; EG: MIN *
|
||||
; SI-SAFE: v_min_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
|
||||
; SI-NONAN: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
|
||||
define amdgpu_kernel void @s_test_fmin_legacy_subreg_inputs_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 {
|
||||
; GCN-SAFE: v_min_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GCN-NONAN: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
|
||||
define amdgpu_kernel void @s_test_fmin_legacy_subreg_inputs_f32(float addrspace(1)* %out, <4 x float> %reg0) #0 {
|
||||
%r0 = extractelement <4 x float> %reg0, i32 0
|
||||
%r1 = extractelement <4 x float> %reg0, i32 1
|
||||
%r2 = fcmp uge float %r0, %r1
|
||||
%r3 = select i1 %r2, float %r1, float %r0
|
||||
%vec = insertelement <4 x float> undef, float %r3, i32 0
|
||||
store <4 x float> %vec, <4 x float> addrspace(1)* %out, align 16
|
||||
store float %r3, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32:
|
||||
; SI-DAG: s_load_dwordx2 s{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; GCN-DAG: s_load_dwordx2 s{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
|
||||
; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], s[[B]]
|
||||
; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], s[[B]]
|
||||
|
||||
; SI-SAFE: v_min_legacy_f32_e64 {{v[0-9]+}}, [[VB]], s[[A]]
|
||||
; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, s[[A]], [[VB]]
|
||||
; GCN-SAFE: v_min_legacy_f32_e64 {{v[0-9]+}}, [[VB]], s[[A]]
|
||||
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, s[[A]], [[VB]]
|
||||
|
||||
define amdgpu_kernel void @s_test_fmin_legacy_ule_f32(float addrspace(1)* %out, float %a, float %b) #0 {
|
||||
%cmp = fcmp ule float %a, %b
|
||||
|
|
@ -37,11 +36,28 @@ define amdgpu_kernel void @s_test_fmin_legacy_ule_f32(float addrspace(1)* %out,
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_ule_f32
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; GCN-LABEL: {{^}}s_test_fmin_legacy_ule_f32_nnan_src:
|
||||
; GCN: s_load_dwordx2 s{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
|
||||
; GCN-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[A]], 1.0
|
||||
; GCN-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[B]], 2.0
|
||||
|
||||
; GCN-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
|
||||
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
|
||||
define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_nnan_src(float addrspace(1)* %out, float %a, float %b) #0 {
|
||||
%a.nnan = fadd nnan float %a, 1.0
|
||||
%b.nnan = fadd nnan float %b, 2.0
|
||||
%cmp = fcmp ule float %a.nnan, %b.nnan
|
||||
%val = select i1 %cmp, float %a.nnan, float %b.nnan
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_fmin_legacy_ule_f32:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
define amdgpu_kernel void @test_fmin_legacy_ule_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
|
||||
|
|
@ -56,11 +72,11 @@ define amdgpu_kernel void @test_fmin_legacy_ule_f32(float addrspace(1)* %out, fl
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_ole_f32
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
define amdgpu_kernel void @test_fmin_legacy_ole_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
|
||||
|
|
@ -75,11 +91,11 @@ define amdgpu_kernel void @test_fmin_legacy_ole_f32(float addrspace(1)* %out, fl
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_olt_f32
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; FUNC-LABEL: {{^}}test_fmin_legacy_olt_f32:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
define amdgpu_kernel void @test_fmin_legacy_olt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
|
||||
|
|
@ -94,11 +110,11 @@ define amdgpu_kernel void @test_fmin_legacy_olt_f32(float addrspace(1)* %out, fl
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_ult_f32
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; FUNC-LABEL: {{^}}test_fmin_legacy_ult_f32:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
define amdgpu_kernel void @test_fmin_legacy_ult_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
|
||||
|
|
@ -114,10 +130,10 @@ define amdgpu_kernel void @test_fmin_legacy_ult_f32(float addrspace(1)* %out, fl
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v1f32:
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
|
||||
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
|
||||
define amdgpu_kernel void @test_fmin_legacy_ult_v1f32(<1 x float> addrspace(1)* %out, <1 x float> addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr <1 x float>, <1 x float> addrspace(1)* %in, i32 %tid
|
||||
|
|
@ -133,13 +149,13 @@ define amdgpu_kernel void @test_fmin_legacy_ult_v1f32(<1 x float> addrspace(1)*
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v2f32:
|
||||
; SI: buffer_load_dwordx2
|
||||
; SI: buffer_load_dwordx2
|
||||
; SI-SAFE: v_min_legacy_f32_e32
|
||||
; SI-SAFE: v_min_legacy_f32_e32
|
||||
; GCN: buffer_load_dwordx2
|
||||
; GCN: buffer_load_dwordx2
|
||||
; GCN-SAFE: v_min_legacy_f32_e32
|
||||
; GCN-SAFE: v_min_legacy_f32_e32
|
||||
|
||||
; SI-NONAN: v_min_f32_e32
|
||||
; SI-NONAN: v_min_f32_e32
|
||||
; GCN-NONAN: v_min_f32_e32
|
||||
; GCN-NONAN: v_min_f32_e32
|
||||
define amdgpu_kernel void @test_fmin_legacy_ult_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %tid
|
||||
|
|
@ -155,13 +171,13 @@ define amdgpu_kernel void @test_fmin_legacy_ult_v2f32(<2 x float> addrspace(1)*
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v3f32:
|
||||
; SI-SAFE: v_min_legacy_f32_e32
|
||||
; SI-SAFE: v_min_legacy_f32_e32
|
||||
; SI-SAFE: v_min_legacy_f32_e32
|
||||
; GCN-SAFE: v_min_legacy_f32_e32
|
||||
; GCN-SAFE: v_min_legacy_f32_e32
|
||||
; GCN-SAFE: v_min_legacy_f32_e32
|
||||
|
||||
; SI-NONAN: v_min_f32_e32
|
||||
; SI-NONAN: v_min_f32_e32
|
||||
; SI-NONAN: v_min_f32_e32
|
||||
; GCN-NONAN: v_min_f32_e32
|
||||
; GCN-NONAN: v_min_f32_e32
|
||||
; GCN-NONAN: v_min_f32_e32
|
||||
define amdgpu_kernel void @test_fmin_legacy_ult_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr <3 x float>, <3 x float> addrspace(1)* %in, i32 %tid
|
||||
|
|
@ -176,14 +192,14 @@ define amdgpu_kernel void @test_fmin_legacy_ult_v3f32(<3 x float> addrspace(1)*
|
|||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @test_fmin_legacy_ole_f32_multi_use
|
||||
; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-NOT: v_min
|
||||
; SI: v_cmp_le_f32
|
||||
; SI-NEXT: v_cndmask_b32
|
||||
; SI-NOT: v_min
|
||||
; SI: s_endpgm
|
||||
; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32_multi_use:
|
||||
; GCN: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; GCN: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; GCN-NOT: v_min
|
||||
; GCN: v_cmp_le_f32
|
||||
; GCN-NEXT: v_cndmask_b32
|
||||
; GCN-NOT: v_min
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @test_fmin_legacy_ole_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() #1
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
|
||||
|
|
|
|||
Loading…
Reference in New Issue