DAG: Don't use ABI copies in some contexts
If an ABI-like value is used in a different block, the type split used is not necessarily the same as the call's ABI. The value is used through an intermediate copy virtual registers from the other block. This resulted in copies with inconsistent sizes later. Fixes regressions since r338197 when AMDGPU started splitting vector types for calls. llvm-svn: 341018
This commit is contained in:
Matt Arsenault
parent
fcd552999f
commit
167601e629
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@ -1178,7 +1178,8 @@ SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
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unsigned InReg = It->second;
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RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
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DAG.getDataLayout(), InReg, Ty, getABIRegCopyCC(V));
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DAG.getDataLayout(), InReg, Ty,
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None); // This is not an ABI copy.
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SDValue Chain = DAG.getEntryNode();
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Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
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V);
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@ -8696,7 +8697,7 @@ SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
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// notional registers required by the type.
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RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(),
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getABIRegCopyCC(V));
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None); // This is not an ABI copy.
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SDValue Chain = DAG.getEntryNode();
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ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
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@ -0,0 +1,176 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; SelectionDAG builder was using the IR value kind to decide how to
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; split the types for copyToRegs/copyFromRegs in all contexts. This
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; was incorrect if the ABI-like value such as a call was used outside
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; of the block. The value in that case is not used directly, but
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; through another set of copies to potentially different register
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; types in the parent block.
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; This would then end up producing inconsistent pairs of copies with
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; the wrong sizes when the vector type result from the call was split
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; into multiple pieces, but expected to be a single register in the
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; cross-block copy.
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;
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; This isn't exactly ideal for AMDGPU, since in reality the
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; intermediate vector register type is undesirable anyway, but it
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; requires more work to be able to split all vector copies in all
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; contexts.
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;
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; This was only an issue if the value was used directly in another
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; block. If there was an intermediate operation or a phi it was fine,
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; since that didn't look like an ABI copy.
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define float @call_split_type_used_outside_block_v2f32() #0 {
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; GCN-LABEL: call_split_type_used_outside_block_v2f32:
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; GCN: ; %bb.0: ; %bb0
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s5, s32
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Spill
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; GCN-NEXT: v_writelane_b32 v32, s33, 0
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; GCN-NEXT: v_writelane_b32 v32, s34, 1
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: v_writelane_b32 v32, s35, 2
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; GCN-NEXT: s_getpc_b64 s[6:7]
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; GCN-NEXT: s_add_u32 s6, s6, func_v2f32@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s7, s7, func_v2f32@rel32@hi+4
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; GCN-NEXT: s_mov_b64 s[34:35], s[30:31]
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; GCN-NEXT: s_mov_b32 s33, s5
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; GCN-NEXT: s_swappc_b64 s[30:31], s[6:7]
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; GCN-NEXT: s_mov_b32 s5, s33
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; GCN-NEXT: s_mov_b64 s[30:31], s[34:35]
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; GCN-NEXT: v_readlane_b32 s35, v32, 2
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; GCN-NEXT: v_readlane_b32 s34, v32, 1
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; GCN-NEXT: v_readlane_b32 s33, v32, 0
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Reload
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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bb0:
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%split.ret.type = call <2 x float> @func_v2f32()
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br label %bb1
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bb1:
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%extract = extractelement <2 x float> %split.ret.type, i32 0
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ret float %extract
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}
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define float @call_split_type_used_outside_block_v3f32() #0 {
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; GCN-LABEL: call_split_type_used_outside_block_v3f32:
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; GCN: ; %bb.0: ; %bb0
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s5, s32
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Spill
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; GCN-NEXT: v_writelane_b32 v32, s33, 0
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; GCN-NEXT: v_writelane_b32 v32, s34, 1
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: v_writelane_b32 v32, s35, 2
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; GCN-NEXT: s_getpc_b64 s[6:7]
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; GCN-NEXT: s_add_u32 s6, s6, func_v3f32@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s7, s7, func_v3f32@rel32@hi+4
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; GCN-NEXT: s_mov_b64 s[34:35], s[30:31]
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; GCN-NEXT: s_mov_b32 s33, s5
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; GCN-NEXT: s_swappc_b64 s[30:31], s[6:7]
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; GCN-NEXT: s_mov_b32 s5, s33
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; GCN-NEXT: s_mov_b64 s[30:31], s[34:35]
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; GCN-NEXT: v_readlane_b32 s35, v32, 2
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; GCN-NEXT: v_readlane_b32 s34, v32, 1
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; GCN-NEXT: v_readlane_b32 s33, v32, 0
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Reload
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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bb0:
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%split.ret.type = call <3 x float> @func_v3f32()
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br label %bb1
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bb1:
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%extract = extractelement <3 x float> %split.ret.type, i32 0
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ret float %extract
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}
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define half @call_split_type_used_outside_block_v4f16() #0 {
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; GCN-LABEL: call_split_type_used_outside_block_v4f16:
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; GCN: ; %bb.0: ; %bb0
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s5, s32
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Spill
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; GCN-NEXT: v_writelane_b32 v32, s33, 0
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; GCN-NEXT: v_writelane_b32 v32, s34, 1
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: v_writelane_b32 v32, s35, 2
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; GCN-NEXT: s_getpc_b64 s[6:7]
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; GCN-NEXT: s_add_u32 s6, s6, func_v4f16@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s7, s7, func_v4f16@rel32@hi+4
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; GCN-NEXT: s_mov_b64 s[34:35], s[30:31]
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; GCN-NEXT: s_mov_b32 s33, s5
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; GCN-NEXT: s_swappc_b64 s[30:31], s[6:7]
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; GCN-NEXT: s_mov_b32 s5, s33
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; GCN-NEXT: s_mov_b64 s[30:31], s[34:35]
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; GCN-NEXT: v_readlane_b32 s35, v32, 2
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; GCN-NEXT: v_readlane_b32 s34, v32, 1
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; GCN-NEXT: v_readlane_b32 s33, v32, 0
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Reload
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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bb0:
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%split.ret.type = call <4 x half> @func_v4f16()
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br label %bb1
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bb1:
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%extract = extractelement <4 x half> %split.ret.type, i32 0
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ret half %extract
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}
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define { i32, half } @call_split_type_used_outside_block_struct() #0 {
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; GCN-LABEL: call_split_type_used_outside_block_struct:
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; GCN: ; %bb.0: ; %bb0
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s5, s32
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Spill
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; GCN-NEXT: v_writelane_b32 v32, s33, 0
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; GCN-NEXT: v_writelane_b32 v32, s34, 1
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: v_writelane_b32 v32, s35, 2
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; GCN-NEXT: s_getpc_b64 s[6:7]
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; GCN-NEXT: s_add_u32 s6, s6, func_struct@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s7, s7, func_struct@rel32@hi+4
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; GCN-NEXT: s_mov_b64 s[34:35], s[30:31]
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; GCN-NEXT: s_mov_b32 s33, s5
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; GCN-NEXT: s_swappc_b64 s[30:31], s[6:7]
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; GCN-NEXT: s_mov_b32 s5, s33
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; GCN-NEXT: s_mov_b64 s[30:31], s[34:35]
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; GCN-NEXT: v_readlane_b32 s35, v32, 2
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; GCN-NEXT: v_readlane_b32 s34, v32, 1
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; GCN-NEXT: v_readlane_b32 s33, v32, 0
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Reload
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; GCN-NEXT: v_mov_b32_e32 v1, v4
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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bb0:
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%split.ret.type = call { <4 x i32>, <4 x half> } @func_struct()
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br label %bb1
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bb1:
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%val0 = extractvalue { <4 x i32>, <4 x half> } %split.ret.type, 0
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%val1 = extractvalue { <4 x i32>, <4 x half> } %split.ret.type, 1
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%extract0 = extractelement <4 x i32> %val0, i32 0
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%extract1 = extractelement <4 x half> %val1, i32 0
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%ins0 = insertvalue { i32, half } undef, i32 %extract0, 0
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%ins1 = insertvalue { i32, half } %ins0, half %extract1, 1
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ret { i32, half } %ins1
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}
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declare <2 x float> @func_v2f32() #0
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declare <3 x float> @func_v3f32() #0
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declare <4 x float> @func_v4f32() #0
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declare <4 x half> @func_v4f16() #0
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declare { <4 x i32>, <4 x half> } @func_struct() #0
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attributes #0 = { nounwind}
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