AMDGPU: Combine and of seto/setuo and fp_class
Clear the nan (or non-nan) test bits from the mask. llvm-svn: 339462
This commit is contained in:
Matt Arsenault
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d35f46caf1
commit
3dcf4ce435
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@ -6429,6 +6429,29 @@ SDValue SITargetLowering::performAndCombine(SDNode *N,
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}
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}
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if (RHS.getOpcode() == ISD::SETCC && LHS.getOpcode() == AMDGPUISD::FP_CLASS)
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std::swap(LHS, RHS);
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if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == AMDGPUISD::FP_CLASS &&
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RHS.hasOneUse()) {
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ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
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// and (fcmp seto), (fp_class x, mask) -> fp_class x, mask & ~(p_nan | n_nan)
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// and (fcmp setuo), (fp_class x, mask) -> fp_class x, mask & (p_nan | n_nan)
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const ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
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if ((LCC == ISD::SETO || LCC == ISD::SETUO) && Mask &&
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(RHS.getOperand(0) == LHS.getOperand(0) &&
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LHS.getOperand(0) == LHS.getOperand(1))) {
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const unsigned OrdMask = SIInstrFlags::S_NAN | SIInstrFlags::Q_NAN;
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unsigned NewMask = LCC == ISD::SETO ?
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Mask->getZExtValue() & ~OrdMask :
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Mask->getZExtValue() & OrdMask;
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SDLoc DL(N);
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return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1, RHS.getOperand(0),
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DAG.getConstant(NewMask, DL, MVT::i32));
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}
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}
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if (VT == MVT::i32 &&
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(RHS.getOpcode() == ISD::SIGN_EXTEND || LHS.getOpcode() == ISD::SIGN_EXTEND)) {
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// and x, (sext cc from i1) => select cc, x, 0
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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declare float @llvm.fabs.f32(float) #1
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declare double @llvm.fabs.f64(double) #1
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@ -124,14 +124,11 @@ define amdgpu_kernel void @test_isfinite_not_pattern_3(i32 addrspace(1)* nocaptu
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ret void
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}
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; Wrong unordered compare
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; GCN-LABEL: {{^}}test_isfinite_pattern_4:
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; GCN-DAG: s_load_dword [[X:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1f8
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; GCN-DAG: v_cmp_o_f32_e64 [[ORD:s\[[0-9]+:[0-9]+\]]], [[X]], [[X]]
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; GCN-DAG: v_cmp_class_f32_e32 vcc, [[X]], [[K]]
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; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[ORD]], vcc
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[AND]]
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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define amdgpu_kernel void @test_isfinite_pattern_4(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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@ -142,5 +139,46 @@ define amdgpu_kernel void @test_isfinite_pattern_4(i32 addrspace(1)* nocapture %
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ret void
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}
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; GCN-LABEL: {{^}}test_isfinite_pattern_4_commute_and:
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; GCN-DAG: s_load_dword [[X:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1f8
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; GCN-DAG: v_cmp_class_f32_e32 vcc, [[X]], [[K]]
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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define amdgpu_kernel void @test_isfinite_pattern_4_commute_and(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp one float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ninf, %ord
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_not_isfinite_pattern_4_wrong_ord_test:
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; GCN-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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; GCN-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x14|0x50}}
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1f8
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; GCN-DAG: v_mov_b32_e32 [[VY:v[0-9]+]], [[Y]]
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; SI-DAG: v_cmp_o_f32_e32 vcc, [[X]], [[VY]]
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; SI-DAG: v_cmp_class_f32_e64 [[CLASS:s\[[0-9]+:[0-9]+\]]], [[X]], [[K]]
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; SI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CLASS]]
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; VI-DAG: v_cmp_o_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[X]], [[VY]]
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; VI-DAG: v_cmp_class_f32_e32 vcc, [[X]], [[K]]
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; VI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP]], vcc
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[AND]]
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define amdgpu_kernel void @test_not_isfinite_pattern_4_wrong_ord_test(i32 addrspace(1)* nocapture %out, float %x, [8 x i32], float %y) #0 {
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%ord = fcmp ord float %x, %y
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp one float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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@ -507,5 +507,42 @@ define amdgpu_kernel void @test_class_undef_f32(i32 addrspace(1)* %out, float %a
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ret void
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}
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; SI-LABEL: {{^}}test_fold_and_ord:
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; SI: s_waitcnt
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; SI-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 32{{$}}
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; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]
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; SI-NEXT: s_setpc_b64
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define i1 @test_fold_and_ord(float %a) {
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%class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1
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%ord = fcmp ord float %a, %a
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%and = and i1 %ord, %class
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ret i1 %and
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}
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; SI-LABEL: {{^}}test_fold_and_unord:
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; SI: s_waitcnt
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; SI-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 3{{$}}
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; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]
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; SI-NEXT: s_setpc_b64
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define i1 @test_fold_and_unord(float %a) {
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%class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1
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%ord = fcmp uno float %a, %a
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%and = and i1 %ord, %class
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ret i1 %and
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}
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; SI-LABEL: {{^}}test_fold_and_ord_multi_use:
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; SI: v_cmp_class
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; SI-NOT: v_cmp_class
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; SI: v_cmp_o
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; SI: s_and_b64
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define i1 @test_fold_and_ord_multi_use(float %a) {
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%class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1
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store volatile i1 %class, i1 addrspace(1)* undef
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%ord = fcmp ord float %a, %a
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%and = and i1 %ord, %class
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ret i1 %and
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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