AMDGPU: Stop trying to extend arguments for clover
This was trying to replace i8/i16 arguments with i32, which was broken and no longer necessary. llvm-svn: 338193
This commit is contained in:
Matt Arsenault
parent
fc4b0fe0a2
commit
72b0e38b26
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@ -945,11 +945,7 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
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unsigned NumRegs =
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getNumRegistersForCallingConv(Ctx, ArgVT);
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if (!Subtarget->isAmdHsaOS() &&
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(ArgVT == MVT::i16 || ArgVT == MVT::i8 || ArgVT == MVT::f16)) {
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// The ABI says the caller will extend these values to 32-bits.
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MemVT = ArgVT.isInteger() ? MVT::i32 : MVT::f32;
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} else if (NumRegs == 1) {
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if (NumRegs == 1) {
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// This argument is not split, so the IR type is the memory type.
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if (ArgVT.isExtended()) {
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// We have an extended type, like i24, so we should just use the
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@ -100,16 +100,6 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
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unsigned Size = DL.getTypeSizeInBits(ArgTy);
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unsigned AllocSize = DL.getTypeAllocSize(ArgTy);
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// Clover seems to always pad i8/i16 to i32, but doesn't properly align
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// them?
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// Make sure the struct elements have correct size and alignment for ext
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// args. These seem to be padded up to 4-bytes but not correctly aligned.
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bool IsExtArg = AllocSize < 32 && (Arg.hasZExtAttr() || Arg.hasSExtAttr()) &&
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!ST.isAmdHsaOS();
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if (IsExtArg)
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AllocSize = 4;
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uint64_t EltOffset = alignTo(ExplicitArgOffset, Align) + BaseOffset;
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ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize;
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@ -164,8 +154,6 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
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ArgPtr->getName() + ".cast");
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}
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assert((!IsExtArg || !IsV3) && "incompatible situation");
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if (IsV3 && Size >= 32) {
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V4Ty = VectorType::get(VT->getVectorElementType(), 4);
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// Use the hack that clang uses to avoid SelectionDAG ruining v3 loads
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@ -212,20 +200,6 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
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// TODO: Convert noalias arg to !noalias
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if (Size < 32 && !ArgTy->isAggregateType()) {
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if (IsExtArg && OffsetDiff == 0) {
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Type *I32Ty = Builder.getInt32Ty();
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bool IsSext = Arg.hasSExtAttr();
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Metadata *LowAndHigh[] = {
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ConstantAsMetadata::get(
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ConstantInt::get(I32Ty, IsSext ? minIntN(Size) : 0)),
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ConstantAsMetadata::get(
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ConstantInt::get(I32Ty,
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IsSext ? maxIntN(Size) + 1 : maxUIntN(Size) + 1))
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};
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Load->setMetadata(LLVMContext::MD_range, MDNode::get(Ctx, LowAndHigh));
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}
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Value *ExtractBits = OffsetDiff == 0 ?
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Load : Builder.CreateLShr(Load, OffsetDiff * 8);
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@ -1,19 +1,28 @@
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; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=SI,GCN,MESA-GCN,FUNC %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefix=EG --check-prefix=FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=EG --check-prefix=FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=EG,EGCM,FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=CM,EGCM,FUNC %s
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; FUNC-LABEL: {{^}}i8_arg:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff
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; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8
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; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff
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; EG: LSHR T0.X, KC0[2].Y, literal.x,
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; EG-NEXT: MOV * T1.X, KC0[2].Z,
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; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; CM: LSHR * T0.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; CM-NEXT: MOV * T1.X, KC0[2].Z,
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define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
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%ext = zext i8 %in to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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@ -23,12 +32,21 @@ define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) noun
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; FUNC-LABEL: {{^}}i8_zext_arg:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
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; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
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; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8
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; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff
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; EG: BFE_INT T0.X, T0.X, 0.0, literal.x,
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; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
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; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)
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; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x,
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; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
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%ext = zext i8 %in to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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@ -38,7 +56,6 @@ define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zero
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; FUNC-LABEL: {{^}}i8_sext_arg:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
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; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
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@ -46,6 +63,16 @@ define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zero
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; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8
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; HSA-VI: s_sext_i32_i8 s{{[0-9]+}}, [[VAL]]
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; HSA-VI: flat_store_dword
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; EG: BFE_INT T0.X, T0.X, 0.0, literal.x,
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; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
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; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)
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; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x,
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; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
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%ext = sext i8 %in to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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@ -56,7 +83,6 @@ define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 sign
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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@ -65,6 +91,15 @@ define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 sign
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; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8
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; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}}
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; HSA-VI: flat_store_dword
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; EG: LSHR T0.X, KC0[2].Y, literal.x,
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; EG-NEXT: MOV * T1.X, KC0[2].Z,
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; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; CM: LSHR * T0.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; CM-NEXT: MOV * T1.X, KC0[2].Z,
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define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
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%ext = zext i16 %in to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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@ -75,13 +110,21 @@ define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) no
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
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; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
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; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8
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; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}}
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; HSA-VI: flat_store_dword
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; EG: BFE_INT T0.X, T0.X, 0.0, literal.x,
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; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
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; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45)
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; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x,
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; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
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%ext = zext i16 %in to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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@ -92,7 +135,6 @@ define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 ze
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
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; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
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@ -100,6 +142,15 @@ define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 ze
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; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8
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; HSA-VI: s_sext_i32_i16 s{{[0-9]+}}, [[VAL]]
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; HSA-VI: flat_store_dword
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; EG: BFE_INT T0.X, T0.X, 0.0, literal.x,
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; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
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; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45)
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; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x,
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; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
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%ext = sext i16 %in to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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@ -110,7 +161,7 @@ define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 si
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z
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; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z
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; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
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; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
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; HSA-VI: s_load_dword s{{[0-9]}}, s[4:5], 0x8
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@ -123,7 +174,7 @@ entry:
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; FUNC-LABEL: {{^}}f32_arg:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z
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; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z
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; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
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; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8
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@ -137,8 +188,8 @@ entry:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: VTX_READ_8
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; EG: VTX_READ_8
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; EGCM: VTX_READ_8
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; EGCM: VTX_READ_8
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; GCN: s_load_dword s
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; GCN-NOT: {{buffer|flat|global}}_load_
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@ -152,8 +203,8 @@ entry:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG: VTX_READ_16
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; EG: VTX_READ_16
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; EGCM: VTX_READ_16
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; EGCM: VTX_READ_16
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; SI: s_load_dword s{{[0-9]+}}, s[0:1], 0xb
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; MESA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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@ -168,8 +219,8 @@ entry:
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; HSA-VI: kernarg_segment_byte_size = 16
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; HSA-VI: kernarg_segment_alignment = 4
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; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
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; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
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; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
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; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
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; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
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; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
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; HSA-VI: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8
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@ -183,8 +234,8 @@ entry:
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; HSA-VI: kernarg_segment_byte_size = 16
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; HSA-VI: kernarg_segment_alignment = 4
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; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
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; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
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; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
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; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
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; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
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; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[4:5], 0x8
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@ -198,9 +249,9 @@ entry:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
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; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
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; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
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; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
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; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
|
||||
; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
|
||||
|
||||
; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
|
||||
|
|
@ -216,9 +267,9 @@ entry:
|
|||
; HSA-VI: kernarg_segment_byte_size = 16
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
|
||||
; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
|
||||
; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
|
||||
; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
|
||||
; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
|
||||
; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
|
||||
; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
|
||||
|
||||
; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
|
||||
|
|
@ -233,9 +284,9 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v3i32_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 32
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
|
||||
; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
|
||||
; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
|
||||
|
|
@ -248,9 +299,9 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v3f32_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 32
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
|
||||
; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
|
||||
; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
|
||||
|
|
@ -263,10 +314,10 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v4i8_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 12
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
|
||||
; GCN-DAG: s_load_dwordx2 s
|
||||
; GCN-DAG: s_load_dword s
|
||||
|
|
@ -279,10 +330,10 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v4i16_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 16
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
|
||||
; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0xb
|
||||
; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x9
|
||||
|
|
@ -305,10 +356,10 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v4i32_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 32
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
|
||||
|
||||
; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
|
||||
; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
|
||||
|
|
@ -322,10 +373,10 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v4f32_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 32
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
|
||||
; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
|
||||
; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
|
||||
; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
|
||||
|
|
@ -339,14 +390,14 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v8i8_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 16
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
|
||||
; SI-NOT: {{buffer|flat|global}}_load
|
||||
; SI: s_load_dwordx2 s
|
||||
|
|
@ -367,14 +418,14 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v8i16_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 32
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
|
||||
; SI: s_load_dwordx4
|
||||
; SI-NEXT: s_load_dwordx2
|
||||
|
|
@ -393,14 +444,14 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v8i32_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 64
|
||||
; HSA-VI: kernarg_segment_alignment = 5
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
|
||||
|
||||
; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
|
||||
; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44
|
||||
|
|
@ -414,14 +465,14 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v8f32_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 64
|
||||
; HSA-VI: kernarg_segment_alignment = 5
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
|
||||
; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
|
||||
define amdgpu_kernel void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind {
|
||||
entry:
|
||||
|
|
@ -434,22 +485,22 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v16i8_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 32
|
||||
; HSA-VI: kernarg_segment_alignment = 4
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
; EGCM: VTX_READ_8
|
||||
|
||||
; SI: s_load_dwordx4 s
|
||||
; SI-NEXT: s_load_dwordx2 s
|
||||
|
|
@ -470,23 +521,23 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v16i16_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 64
|
||||
; HSA-VI: kernarg_segment_alignment = 5
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
; EGCM: VTX_READ_16
|
||||
|
||||
; SI: s_load_dwordx8 s
|
||||
; SI-NEXT: s_load_dwordx2 s
|
||||
|
|
@ -505,22 +556,22 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v16i32_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 128
|
||||
; HSA-VI: kernarg_segment_alignment = 6
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
|
||||
; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19
|
||||
; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64
|
||||
; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40
|
||||
|
|
@ -533,22 +584,22 @@ entry:
|
|||
; FUNC-LABEL: {{^}}v16f32_arg:
|
||||
; HSA-VI: kernarg_segment_byte_size = 128
|
||||
; HSA-VI: kernarg_segment_alignment = 6
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
|
||||
; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
|
||||
; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
|
||||
; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19
|
||||
; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64
|
||||
; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ define amdgpu_kernel void @kern_zeroext_i8(i8 zeroext %arg) #0 {
|
|||
; MESA-NEXT: [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
|
||||
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 36
|
||||
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
|
||||
; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !1, !invariant.load !0
|
||||
; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
|
||||
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
|
||||
; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1
|
||||
; MESA-NEXT: ret void
|
||||
|
|
@ -121,7 +121,7 @@ define amdgpu_kernel void @kern_zeroext_i16(i16 zeroext %arg) #0 {
|
|||
; MESA-NEXT: [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
|
||||
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 36
|
||||
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
|
||||
; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !2, !invariant.load !0
|
||||
; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
|
||||
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||||
; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1
|
||||
; MESA-NEXT: ret void
|
||||
|
|
@ -144,7 +144,7 @@ define amdgpu_kernel void @kern_signext_i8(i8 signext %arg) #0 {
|
|||
; MESA-NEXT: [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
|
||||
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 36
|
||||
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
|
||||
; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !3, !invariant.load !0
|
||||
; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
|
||||
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
|
||||
; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1
|
||||
; MESA-NEXT: ret void
|
||||
|
|
@ -167,7 +167,7 @@ define amdgpu_kernel void @kern_signext_i16(i16 signext %arg) #0 {
|
|||
; MESA-NEXT: [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
|
||||
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 36
|
||||
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
|
||||
; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !4, !invariant.load !0
|
||||
; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
|
||||
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||||
; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1
|
||||
; MESA-NEXT: ret void
|
||||
|
|
@ -1160,7 +1160,7 @@ define amdgpu_kernel void @kern_global_ptr_dereferencable(i8 addrspace(1)* deref
|
|||
; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
|
||||
; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 36
|
||||
; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
|
||||
; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable !5
|
||||
; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable !1
|
||||
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef
|
||||
; MESA-NEXT: ret void
|
||||
;
|
||||
|
|
@ -1181,7 +1181,7 @@ define amdgpu_kernel void @kern_global_ptr_dereferencable_or_null(i8 addrspace(1
|
|||
; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
|
||||
; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 36
|
||||
; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
|
||||
; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable_or_null !6
|
||||
; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable_or_null !2
|
||||
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef
|
||||
; MESA-NEXT: ret void
|
||||
;
|
||||
|
|
@ -1223,7 +1223,7 @@ define amdgpu_kernel void @kern_align32_global_ptr(i8 addrspace(1)* align 1024 %
|
|||
; MESA-NEXT: [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
|
||||
; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36
|
||||
; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
|
||||
; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !align !7
|
||||
; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !align !3
|
||||
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef
|
||||
; MESA-NEXT: ret void
|
||||
;
|
||||
|
|
@ -1432,17 +1432,7 @@ attributes #0 = { nounwind "target-cpu"="kaveri" }
|
|||
attributes #1 = { nounwind "target-cpu"="kaveri" "amdgpu-implicitarg-num-bytes"="40" }
|
||||
attributes #2 = { nounwind "target-cpu"="tahiti" }
|
||||
|
||||
; HSA: 0 = !{}
|
||||
; HSA: !1 = !{i64 42}
|
||||
; HSA: !2 = !{i64 128}
|
||||
; HSA: !3 = !{i64 1024}
|
||||
|
||||
|
||||
; MESA: !0 = !{}
|
||||
; MESA: !1 = !{i32 0, i32 256}
|
||||
; MESA: !2 = !{i32 0, i32 65536}
|
||||
; MESA: !3 = !{i32 -128, i32 128}
|
||||
; MESA: !4 = !{i32 -32768, i32 32768}
|
||||
; MESA: !5 = !{i64 42}
|
||||
; MESA: !6 = !{i64 128}
|
||||
; MESA: !7 = !{i64 1024}
|
||||
; GCN: 0 = !{}
|
||||
; GCN: !1 = !{i64 42}
|
||||
; GCN: !2 = !{i64 128}
|
||||
; GCN: !3 = !{i64 1024}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=EG %s
|
||||
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=CM %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
|
||||
; RUN: llc -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM %s
|
||||
|
||||
; Loosely based on test/CodeGen/{X86,AArch64}/extract-lowbits.ll,
|
||||
; but with all 64-bit tests, and tests with loads dropped.
|
||||
|
|
@ -15,11 +16,28 @@
|
|||
; Pattern a. 32-bit
|
||||
; ---------------------------------------------------------------------------- ;
|
||||
|
||||
; R600-LABEL: bzhi32_a0:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_a0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_a0:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: ALU clause starting at 4:
|
||||
; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
;
|
||||
; CM-LABEL: bzhi32_a0:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: ALU clause starting at 4:
|
||||
; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
%onebit = shl i32 1, %numlowbits
|
||||
%mask = add nsw i32 %onebit, -1
|
||||
%masked = and i32 %mask, %val
|
||||
|
|
@ -27,11 +45,44 @@ define amdgpu_kernel void @bzhi32_a0(i32 %val, i32 %numlowbits, i32 addrspace(1)
|
|||
ret void
|
||||
}
|
||||
|
||||
; R600-LABEL: bzhi32_a1_indexzext:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_a1_indexzext:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 0, @8, KC0[], KC1[]
|
||||
; EG-NEXT: TEX 0 @6
|
||||
; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: Fetch clause starting at 6:
|
||||
; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
||||
; EG-NEXT: ALU clause starting at 8:
|
||||
; EG-NEXT: MOV * T0.X, 0.0,
|
||||
; EG-NEXT: ALU clause starting at 9:
|
||||
; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
|
||||
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT T0.X, KC0[2].Y, 0.0, PV.W,
|
||||
; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
;
|
||||
; CM-LABEL: bzhi32_a1_indexzext:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 0, @8, KC0[], KC1[]
|
||||
; CM-NEXT: TEX 0 @6
|
||||
; CM-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: Fetch clause starting at 6:
|
||||
; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
||||
; CM-NEXT: ALU clause starting at 8:
|
||||
; CM-NEXT: MOV * T0.X, 0.0,
|
||||
; CM-NEXT: ALU clause starting at 9:
|
||||
; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
|
||||
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T0.X, KC0[2].Y, 0.0, PV.W,
|
||||
; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
%conv = zext i8 %numlowbits to i32
|
||||
%onebit = shl i32 1, %conv
|
||||
%mask = add nsw i32 %onebit, -1
|
||||
|
|
@ -40,11 +91,28 @@ define amdgpu_kernel void @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits,
|
|||
ret void
|
||||
}
|
||||
|
||||
; R600-LABEL: bzhi32_a4_commutative:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_a4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_a4_commutative:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: ALU clause starting at 4:
|
||||
; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
;
|
||||
; CM-LABEL: bzhi32_a4_commutative:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: ALU clause starting at 4:
|
||||
; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
%onebit = shl i32 1, %numlowbits
|
||||
%mask = add nsw i32 %onebit, -1
|
||||
%masked = and i32 %val, %mask ; swapped order
|
||||
|
|
@ -56,11 +124,28 @@ define amdgpu_kernel void @bzhi32_a4_commutative(i32 %val, i32 %numlowbits, i32
|
|||
; Pattern b. 32-bit
|
||||
; ---------------------------------------------------------------------------- ;
|
||||
|
||||
; R600-LABEL: bzhi32_b0:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_b0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_b0:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: ALU clause starting at 4:
|
||||
; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
;
|
||||
; CM-LABEL: bzhi32_b0:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: ALU clause starting at 4:
|
||||
; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
%notmask = shl i32 -1, %numlowbits
|
||||
%mask = xor i32 %notmask, -1
|
||||
%masked = and i32 %mask, %val
|
||||
|
|
@ -68,11 +153,44 @@ define amdgpu_kernel void @bzhi32_b0(i32 %val, i32 %numlowbits, i32 addrspace(1)
|
|||
ret void
|
||||
}
|
||||
|
||||
; R600-LABEL: bzhi32_b1_indexzext:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_b1_indexzext:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 0, @8, KC0[], KC1[]
|
||||
; EG-NEXT: TEX 0 @6
|
||||
; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: Fetch clause starting at 6:
|
||||
; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
||||
; EG-NEXT: ALU clause starting at 8:
|
||||
; EG-NEXT: MOV * T0.X, 0.0,
|
||||
; EG-NEXT: ALU clause starting at 9:
|
||||
; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
|
||||
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT T0.X, KC0[2].Y, 0.0, PV.W,
|
||||
; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
;
|
||||
; CM-LABEL: bzhi32_b1_indexzext:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 0, @8, KC0[], KC1[]
|
||||
; CM-NEXT: TEX 0 @6
|
||||
; CM-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: Fetch clause starting at 6:
|
||||
; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
||||
; CM-NEXT: ALU clause starting at 8:
|
||||
; CM-NEXT: MOV * T0.X, 0.0,
|
||||
; CM-NEXT: ALU clause starting at 9:
|
||||
; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
|
||||
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T0.X, KC0[2].Y, 0.0, PV.W,
|
||||
; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
%conv = zext i8 %numlowbits to i32
|
||||
%notmask = shl i32 -1, %conv
|
||||
%mask = xor i32 %notmask, -1
|
||||
|
|
@ -81,11 +199,28 @@ define amdgpu_kernel void @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits,
|
|||
ret void
|
||||
}
|
||||
|
||||
; R600-LABEL: bzhi32_b4_commutative:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_b4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_b4_commutative:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: ALU clause starting at 4:
|
||||
; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
;
|
||||
; CM-LABEL: bzhi32_b4_commutative:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: ALU clause starting at 4:
|
||||
; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
%notmask = shl i32 -1, %numlowbits
|
||||
%mask = xor i32 %notmask, -1
|
||||
%masked = and i32 %val, %mask ; swapped order
|
||||
|
|
@ -97,11 +232,28 @@ define amdgpu_kernel void @bzhi32_b4_commutative(i32 %val, i32 %numlowbits, i32
|
|||
; Pattern c. 32-bit
|
||||
; ---------------------------------------------------------------------------- ;
|
||||
|
||||
; R600-LABEL: bzhi32_c0:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_c0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_c0:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: ALU clause starting at 4:
|
||||
; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
;
|
||||
; CM-LABEL: bzhi32_c0:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: ALU clause starting at 4:
|
||||
; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
%numhighbits = sub i32 32, %numlowbits
|
||||
%mask = lshr i32 -1, %numhighbits
|
||||
%masked = and i32 %mask, %val
|
||||
|
|
@ -109,17 +261,52 @@ define amdgpu_kernel void @bzhi32_c0(i32 %val, i32 %numlowbits, i32 addrspace(1)
|
|||
ret void
|
||||
}
|
||||
|
||||
; R600-LABEL: bzhi32_c1_indexzext:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: SUB_INT {{\*?}} [[SUBR:T[0-9]+]].[[SUBC:[XYZW]]], literal.x, KC0[2].Z
|
||||
; R600-NEXT: 32
|
||||
; R600-NEXT: AND_INT {{\*?}} {{T[0-9]+}}.[[AND1C:[XYZW]]], {{T[0-9]+|PV}}.[[SUBC]], literal.x
|
||||
; R600-NEXT: 255
|
||||
; R600: LSHR {{\*?}} {{T[0-9]}}.[[LSHRC:[XYZW]]], literal.x, {{T[0-9]+|PV}}.[[AND1C]]
|
||||
; R600-NEXT: -1
|
||||
; R600-NEXT: AND_INT {{[* ]*}}[[RET]], {{T[0-9]+|PV}}.[[LSHRC]], KC0[2].Y
|
||||
define amdgpu_kernel void @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_c1_indexzext:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 0, @8, KC0[], KC1[]
|
||||
; EG-NEXT: TEX 0 @6
|
||||
; EG-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: Fetch clause starting at 6:
|
||||
; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
||||
; EG-NEXT: ALU clause starting at 8:
|
||||
; EG-NEXT: MOV * T0.X, 0.0,
|
||||
; EG-NEXT: ALU clause starting at 9:
|
||||
; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X,
|
||||
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
|
||||
; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
|
||||
; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
|
||||
; EG-NEXT: LSHR * T0.W, literal.x, PV.W,
|
||||
; EG-NEXT: -1(nan), 0(0.000000e+00)
|
||||
; EG-NEXT: AND_INT T0.X, PV.W, KC0[2].Y,
|
||||
; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
;
|
||||
; CM-LABEL: bzhi32_c1_indexzext:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 0, @8, KC0[], KC1[]
|
||||
; CM-NEXT: TEX 0 @6
|
||||
; CM-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: Fetch clause starting at 6:
|
||||
; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
||||
; CM-NEXT: ALU clause starting at 8:
|
||||
; CM-NEXT: MOV * T0.X, 0.0,
|
||||
; CM-NEXT: ALU clause starting at 9:
|
||||
; CM-NEXT: SUB_INT * T0.W, literal.x, T0.X,
|
||||
; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)
|
||||
; CM-NEXT: AND_INT * T0.W, PV.W, literal.x,
|
||||
; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)
|
||||
; CM-NEXT: LSHR * T0.W, literal.x, PV.W,
|
||||
; CM-NEXT: -1(nan), 0(0.000000e+00)
|
||||
; CM-NEXT: AND_INT * T0.X, PV.W, KC0[2].Y,
|
||||
; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
%numhighbits = sub i8 32, %numlowbits
|
||||
%sh_prom = zext i8 %numhighbits to i32
|
||||
%mask = lshr i32 -1, %sh_prom
|
||||
|
|
@ -128,11 +315,28 @@ define amdgpu_kernel void @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits, i32 add
|
|||
ret void
|
||||
}
|
||||
|
||||
; R600-LABEL: bzhi32_c4_commutative:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_c4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_c4_commutative:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: ALU clause starting at 4:
|
||||
; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
;
|
||||
; CM-LABEL: bzhi32_c4_commutative:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: ALU clause starting at 4:
|
||||
; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
%numhighbits = sub i32 32, %numlowbits
|
||||
%mask = lshr i32 -1, %numhighbits
|
||||
%masked = and i32 %val, %mask ; swapped order
|
||||
|
|
@ -144,11 +348,28 @@ define amdgpu_kernel void @bzhi32_c4_commutative(i32 %val, i32 %numlowbits, i32
|
|||
; Pattern d. 32-bit.
|
||||
; ---------------------------------------------------------------------------- ;
|
||||
|
||||
; R600-LABEL: bzhi32_d0:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
|
||||
define amdgpu_kernel void @bzhi32_d0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_d0:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: ALU clause starting at 4:
|
||||
; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
;
|
||||
; CM-LABEL: bzhi32_d0:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: ALU clause starting at 4:
|
||||
; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
|
||||
%numhighbits = sub i32 32, %numlowbits
|
||||
%highbitscleared = shl i32 %val, %numhighbits
|
||||
%masked = lshr i32 %highbitscleared, %numhighbits
|
||||
|
|
@ -156,16 +377,50 @@ define amdgpu_kernel void @bzhi32_d0(i32 %val, i32 %numlowbits, i32 addrspace(1)
|
|||
ret void
|
||||
}
|
||||
|
||||
; R600-LABEL: bzhi32_d1_indexzext:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
|
||||
; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
|
||||
; R600: SUB_INT {{\*?}} [[SUBR:T[0-9]+]].[[SUBC:[XYZW]]], literal.x, KC0[2].Z
|
||||
; R600-NEXT: 32
|
||||
; R600-NEXT: AND_INT {{\*?}} [[AND:T[0-9]+\.[XYZW]]], {{T[0-9]+|PV}}.[[SUBC]], literal.x
|
||||
; R600-NEXT: 255
|
||||
; R600: LSHL {{\*?}} {{T[0-9]}}.[[LSHLC:[XYZW]]], KC0[2].Y, {{T[0-9]+|PV}}.[[AND1C]]
|
||||
; R600: LSHR {{[* ]*}}[[RET]], {{T[0-9]+|PV}}.[[LSHLC]], [[AND]]
|
||||
define amdgpu_kernel void @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) {
|
||||
; EG-LABEL: bzhi32_d1_indexzext:
|
||||
; EG: ; %bb.0:
|
||||
; EG-NEXT: ALU 0, @8, KC0[], KC1[]
|
||||
; EG-NEXT: TEX 0 @6
|
||||
; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]
|
||||
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; EG-NEXT: CF_END
|
||||
; EG-NEXT: PAD
|
||||
; EG-NEXT: Fetch clause starting at 6:
|
||||
; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
||||
; EG-NEXT: ALU clause starting at 8:
|
||||
; EG-NEXT: MOV * T0.X, 0.0,
|
||||
; EG-NEXT: ALU clause starting at 9:
|
||||
; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X,
|
||||
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
|
||||
; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
|
||||
; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
|
||||
; EG-NEXT: LSHL * T1.W, KC0[2].Y, PV.W,
|
||||
; EG-NEXT: LSHR T0.X, PV.W, T0.W,
|
||||
; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
||||
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
;
|
||||
; CM-LABEL: bzhi32_d1_indexzext:
|
||||
; CM: ; %bb.0:
|
||||
; CM-NEXT: ALU 0, @8, KC0[], KC1[]
|
||||
; CM-NEXT: TEX 0 @6
|
||||
; CM-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]
|
||||
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
|
||||
; CM-NEXT: CF_END
|
||||
; CM-NEXT: PAD
|
||||
; CM-NEXT: Fetch clause starting at 6:
|
||||
; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
||||
; CM-NEXT: ALU clause starting at 8:
|
||||
; CM-NEXT: MOV * T0.X, 0.0,
|
||||
; CM-NEXT: ALU clause starting at 9:
|
||||
; CM-NEXT: SUB_INT * T0.W, literal.x, T0.X,
|
||||
; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)
|
||||
; CM-NEXT: AND_INT * T0.W, PV.W, literal.x,
|
||||
; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)
|
||||
; CM-NEXT: LSHL * T1.W, KC0[2].Y, PV.W,
|
||||
; CM-NEXT: LSHR * T0.X, PV.W, T0.W,
|
||||
; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
||||
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
%numhighbits = sub i8 32, %numlowbits
|
||||
%sh_prom = zext i8 %numhighbits to i32
|
||||
%highbitscleared = shl i32 %val, %sh_prom
|
||||
|
|
|
|||
|
|
@ -24,23 +24,12 @@ entry:
|
|||
; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
|
||||
; EG-NOT: MEM_RAT MSKOR
|
||||
|
||||
; IG 0: Get the byte index and truncate the value
|
||||
; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
|
||||
; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
|
||||
; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
|
||||
; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)
|
||||
|
||||
|
||||
; IG 1: Truncate the calculated the shift amount for the mask
|
||||
|
||||
; IG 2: Shift the value and the mask
|
||||
; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
|
||||
; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
|
||||
; EG-NEXT: 255
|
||||
; IG 3: Initialize the Y and Z channels to zero
|
||||
; XXX: An optimal scheduler should merge this into one of the prevous IGs.
|
||||
; EG: MOV T[[RW_GPR]].Y, 0.0
|
||||
; EG: MOV * T[[RW_GPR]].Z, 0.0
|
||||
; EG: VTX_READ_8
|
||||
; EG: AND_INT
|
||||
; EG: AND_INT
|
||||
; EG: LSHL
|
||||
; EG: LSHL
|
||||
; EG: LSHL
|
||||
|
||||
; SIVI: buffer_store_byte
|
||||
; GFX9: global_store_byte
|
||||
|
|
@ -55,27 +44,14 @@ entry:
|
|||
; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
|
||||
; EG-NOT: MEM_RAT MSKOR
|
||||
|
||||
; IG 0: Get the byte index and truncate the value
|
||||
; EG: VTX_READ_16
|
||||
; EG: AND_INT
|
||||
; EG: AND_INT
|
||||
; EG: LSHL
|
||||
; EG: LSHL
|
||||
; EG: LSHL
|
||||
|
||||
|
||||
; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
|
||||
; EG-NEXT: 3(4.203895e-45),
|
||||
|
||||
; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
|
||||
; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
|
||||
|
||||
; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
|
||||
; IG 1: Truncate the calculated the shift amount for the mask
|
||||
|
||||
; IG 2: Shift the value and the mask
|
||||
; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
|
||||
; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
|
||||
; EG-NEXT: 65535
|
||||
; IG 3: Initialize the Y and Z channels to zero
|
||||
; XXX: An optimal scheduler should merge this into one of the prevous IGs.
|
||||
; EG: MOV T[[RW_GPR]].Y, 0.0
|
||||
; EG: MOV * T[[RW_GPR]].Z, 0.0
|
||||
|
||||
; SIVI: buffer_store_short
|
||||
; GFX9: global_store_short
|
||||
define amdgpu_kernel void @store_i16(i16 addrspace(1)* %out, i16 %in) {
|
||||
|
|
|
|||
|
|
@ -32,7 +32,9 @@ entry:
|
|||
; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
|
||||
; EG: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
|
||||
; EG-NEXT: 3(4.203895e-45)
|
||||
; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.x
|
||||
|
||||
|
||||
; EG: LSHL * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], literal.x, PV.W
|
||||
; EG-NEXT: 255(3.573311e-43)
|
||||
|
||||
; EG: NOT_INT
|
||||
|
|
@ -57,12 +59,12 @@ entry:
|
|||
; EG: MOVA_INT * AR.x (MASKED)
|
||||
; EG: MOV [[OLD:T[0-9]\.[XYZW]]], {{.*}}AR.x
|
||||
|
||||
; EG: VTX_READ_16
|
||||
|
||||
; IG 0: Get the byte index and truncate the value
|
||||
; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
|
||||
; EG: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
|
||||
; EG-NEXT: 3(4.203895e-45)
|
||||
; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.x
|
||||
; EG-NEXT: 65535(9.183409e-41)
|
||||
|
||||
; EG: NOT_INT
|
||||
; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]]
|
||||
|
|
|
|||
|
|
@ -51,11 +51,11 @@ define amdgpu_kernel void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a,
|
|||
; GCN: s_load_dword [[A:s[0-9]+]]
|
||||
; GCN: s_load_dword [[B:s[0-9]+]]
|
||||
|
||||
; SI: v_mov_b32_e32 [[V_A:v[0-9]+]], [[A]]
|
||||
; SI: v_cmp_eq_u32_e32 vcc, [[B]], [[V_A]]
|
||||
|
||||
; VI: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]]
|
||||
; VI: v_cmp_eq_u32_e32 vcc, [[A]], [[V_B]]
|
||||
; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
|
||||
; GCN-DAG: s_and_b32 [[MASK_A:s[0-9]+]], [[A]], [[MASK]]
|
||||
; GCN-DAG: s_and_b32 [[MASK_B:s[0-9]+]], [[B]], [[MASK]]
|
||||
; GCN: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]]
|
||||
; GCN: v_cmp_eq_u32_e32 vcc, [[MASK_A]], [[V_B]]
|
||||
|
||||
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
|
||||
; GCN: buffer_store_short [[RESULT]]
|
||||
|
|
|
|||
Loading…
Reference in New Issue