[AMDGPU] Use AssumptionCacheTracker in the divrem32 expansion
Differential Revision: https://reviews.llvm.org/D49761 llvm-svn: 337938
This commit is contained in:
Stanislav Mekhanoshin
parent
cbb4313b1c
commit
7e7268ac1c
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@ -17,6 +17,7 @@
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/AssumptionCache.h"
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#include "llvm/Analysis/DivergenceAnalysis.h"
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#include "llvm/Analysis/Loads.h"
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#include "llvm/Analysis/ValueTracking.h"
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@ -58,6 +59,7 @@ static cl::opt<bool> WidenLoads(
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class AMDGPUCodeGenPrepare : public FunctionPass,
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public InstVisitor<AMDGPUCodeGenPrepare, bool> {
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const GCNSubtarget *ST = nullptr;
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AssumptionCache *AC = nullptr;
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DivergenceAnalysis *DA = nullptr;
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Module *Mod = nullptr;
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bool HasUnsafeFPMath = false;
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@ -134,11 +136,12 @@ class AMDGPUCodeGenPrepare : public FunctionPass,
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bool promoteUniformBitreverseToI32(IntrinsicInst &I) const;
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/// Expands 24 bit div or rem.
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Value* expandDivRem24(IRBuilder<> &Builder, Value *Num, Value *Den,
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Value* expandDivRem24(IRBuilder<> &Builder, BinaryOperator &I,
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Value *Num, Value *Den,
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bool IsDiv, bool IsSigned) const;
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/// Expands 32 bit div or rem.
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Value* expandDivRem32(IRBuilder<> &Builder, Instruction::BinaryOps Opc,
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Value* expandDivRem32(IRBuilder<> &Builder, BinaryOperator &I,
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Value *Num, Value *Den) const;
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/// Widen a scalar load.
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@ -173,6 +176,7 @@ public:
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StringRef getPassName() const override { return "AMDGPU IR optimizations"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<AssumptionCacheTracker>();
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AU.addRequired<DivergenceAnalysis>();
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AU.setPreservesAll();
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}
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@ -500,16 +504,17 @@ static Value* getMulHu(IRBuilder<> &Builder, Value *LHS, Value *RHS) {
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// The fractional part of a float is enough to accurately represent up to
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// a 24-bit signed integer.
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Value* AMDGPUCodeGenPrepare::expandDivRem24(IRBuilder<> &Builder,
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BinaryOperator &I,
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Value *Num, Value *Den,
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bool IsDiv, bool IsSigned) const {
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assert(Num->getType()->isIntegerTy(32));
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const DataLayout &DL = Mod->getDataLayout();
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unsigned LHSSignBits = ComputeNumSignBits(Num, DL);
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unsigned LHSSignBits = ComputeNumSignBits(Num, DL, 0, AC, &I);
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if (LHSSignBits < 9)
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return nullptr;
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unsigned RHSSignBits = ComputeNumSignBits(Den, DL);
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unsigned RHSSignBits = ComputeNumSignBits(Den, DL, 0, AC, &I);
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if (RHSSignBits < 9)
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return nullptr;
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@ -603,8 +608,9 @@ Value* AMDGPUCodeGenPrepare::expandDivRem24(IRBuilder<> &Builder,
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}
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Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
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Instruction::BinaryOps Opc,
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BinaryOperator &I,
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Value *Num, Value *Den) const {
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Instruction::BinaryOps Opc = I.getOpcode();
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assert(Opc == Instruction::URem || Opc == Instruction::UDiv ||
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Opc == Instruction::SRem || Opc == Instruction::SDiv);
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@ -632,7 +638,7 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
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}
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}
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if (Value *Res = expandDivRem24(Builder, Num, Den, IsDiv, IsSigned)) {
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if (Value *Res = expandDivRem24(Builder, I, Num, Den, IsDiv, IsSigned)) {
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Res = Builder.CreateTrunc(Res, Ty);
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return Res;
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}
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@ -767,16 +773,16 @@ bool AMDGPUCodeGenPrepare::visitBinaryOperator(BinaryOperator &I) {
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if (VectorType *VT = dyn_cast<VectorType>(Ty)) {
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NewDiv = UndefValue::get(VT);
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for (unsigned I = 0, E = VT->getNumElements(); I != E; ++I) {
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Value *NumEltI = Builder.CreateExtractElement(Num, I);
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Value *DenEltI = Builder.CreateExtractElement(Den, I);
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Value *NewElt = expandDivRem32(Builder, Opc, NumEltI, DenEltI);
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for (unsigned N = 0, E = VT->getNumElements(); N != E; ++N) {
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Value *NumEltN = Builder.CreateExtractElement(Num, N);
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Value *DenEltN = Builder.CreateExtractElement(Den, N);
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Value *NewElt = expandDivRem32(Builder, I, NumEltN, DenEltN);
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if (!NewElt)
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NewElt = Builder.CreateBinOp(Opc, NumEltI, DenEltI);
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NewDiv = Builder.CreateInsertElement(NewDiv, NewElt, I);
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NewElt = Builder.CreateBinOp(Opc, NumEltN, DenEltN);
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NewDiv = Builder.CreateInsertElement(NewDiv, NewElt, N);
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}
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} else {
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NewDiv = expandDivRem32(Builder, Opc, Num, Den);
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NewDiv = expandDivRem32(Builder, I, Num, Den);
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}
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if (NewDiv) {
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@ -891,6 +897,7 @@ bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
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const AMDGPUTargetMachine &TM = TPC->getTM<AMDGPUTargetMachine>();
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ST = &TM.getSubtarget<GCNSubtarget>(F);
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AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
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DA = &getAnalysis<DivergenceAnalysis>();
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HasUnsafeFPMath = hasUnsafeFPMath(F);
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AMDGPUASI = TM.getAMDGPUAS();
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@ -910,6 +917,7 @@ bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
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INITIALIZE_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE,
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"AMDGPU IR optimizations", false, false)
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INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
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INITIALIZE_PASS_DEPENDENCY(DivergenceAnalysis)
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INITIALIZE_PASS_END(AMDGPUCodeGenPrepare, DEBUG_TYPE, "AMDGPU IR optimizations",
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false, false)
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@ -0,0 +1,43 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck %s
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define amdgpu_kernel void @divrem24_assume(i32 addrspace(1)* %arg, i32 %arg1) {
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; CHECK-LABEL: @divrem24_assume(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[ARG1:%.*]], 42
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
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; CHECK-NEXT: [[TMP0:%.*]] = uitofp i32 [[TMP]] to float
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; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[ARG1]] to float
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; CHECK-NEXT: [[TMP2:%.*]] = fdiv fast float 1.000000e+00, [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.trunc.f32(float [[TMP3]])
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; CHECK-NEXT: [[TMP5:%.*]] = fsub fast float -0.000000e+00, [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP5]], float [[TMP1]], float [[TMP0]])
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; CHECK-NEXT: [[TMP7:%.*]] = fptoui float [[TMP4]] to i32
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; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
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; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.fabs.f32(float [[TMP1]])
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; CHECK-NEXT: [[TMP10:%.*]] = fcmp fast oge float [[TMP8]], [[TMP9]]
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; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 1, i32 0
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; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP7]], [[TMP11]]
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; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], 1023
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP13]] to i64
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG:%.*]], i64 [[TMP4]]
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; CHECK-NEXT: store i32 0, i32 addrspace(1)* [[TMP5]], align 4
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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%tmp2 = icmp ult i32 %arg1, 42
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tail call void @llvm.assume(i1 %tmp2)
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%tmp3 = udiv i32 %tmp, %arg1
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp4
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store i32 0, i32 addrspace(1)* %tmp5, align 4
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ret void
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}
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declare void @llvm.assume(i1)
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declare i32 @llvm.amdgcn.workitem.id.x()
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!0 = !{i32 0, i32 1024}
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