AMDGPU: Remove custom BUILD_VECTOR combine
This was looping in a testcase and removing it now slightly improves a test. llvm-svn: 345560
This commit is contained in:
Matt Arsenault
parent
b0b741efb8
commit
abc4f29f9c
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@ -679,7 +679,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
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setTargetDAGCombine(ISD::BUILD_VECTOR);
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// All memory operations. Some folding on the pointer operand is done to help
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// matching the constant offsets in the addressing modes.
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@ -8133,48 +8132,6 @@ SDValue SITargetLowering::performExtractVectorEltCombine(
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return SDValue();
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}
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static bool convertBuildVectorCastElt(SelectionDAG &DAG,
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SDValue &Lo, SDValue &Hi) {
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if (Hi.getOpcode() == ISD::BITCAST &&
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Hi.getOperand(0).getValueType() == MVT::f16 &&
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(isa<ConstantSDNode>(Lo) || Lo.isUndef())) {
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Lo = DAG.getNode(ISD::BITCAST, SDLoc(Lo), MVT::f16, Lo);
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Hi = Hi.getOperand(0);
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return true;
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}
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return false;
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}
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SDValue SITargetLowering::performBuildVectorCombine(
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SDNode *N, DAGCombinerInfo &DCI) const {
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SDLoc SL(N);
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if (!isTypeLegal(MVT::v2i16))
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return SDValue();
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SelectionDAG &DAG = DCI.DAG;
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EVT VT = N->getValueType(0);
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if (VT == MVT::v2i16) {
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SDValue Lo = N->getOperand(0);
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SDValue Hi = N->getOperand(1);
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// v2i16 build_vector (const|undef), (bitcast f16:$x)
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// -> bitcast (v2f16 build_vector const|undef, $x
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if (convertBuildVectorCastElt(DAG, Lo, Hi)) {
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SDValue NewVec = DAG.getBuildVector(MVT::v2f16, SL, { Lo, Hi });
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return DAG.getNode(ISD::BITCAST, SL, VT, NewVec);
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}
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if (convertBuildVectorCastElt(DAG, Hi, Lo)) {
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SDValue NewVec = DAG.getBuildVector(MVT::v2f16, SL, { Hi, Lo });
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return DAG.getNode(ISD::BITCAST, SL, VT, NewVec);
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}
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}
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return SDValue();
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}
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unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG,
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const SDNode *N0,
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const SDNode *N1) const {
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@ -8783,8 +8740,6 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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}
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case ISD::EXTRACT_VECTOR_ELT:
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return performExtractVectorEltCombine(N, DCI);
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case ISD::BUILD_VECTOR:
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return performBuildVectorCombine(N, DCI);
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}
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return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
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}
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@ -154,7 +154,6 @@ private:
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SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performBuildVectorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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unsigned getFusedOpcode(const SelectionDAG &DAG,
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const SDNode *N0, const SDNode *N1) const;
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@ -0,0 +1,27 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; There was an infinite loop in DAGCombiner from a target build_vector
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; combine and a generic insert_vector_elt combine.
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; GCN-LABEL: {{^}}combine_loop:
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; GCN: flat_load_ushort
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; GCN: flat_store_short
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; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
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define amdgpu_kernel void @combine_loop(i16* %arg) #0 {
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bb:
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br label %bb1
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bb1:
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%tmp = phi <2 x i16> [ <i16 15360, i16 15360>, %bb ], [ %tmp5, %bb1 ]
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%tmp2 = phi half [ 0xH0000, %bb ], [ %tmp8, %bb1 ]
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%tmp3 = load volatile half, half* null, align 536870912
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%tmp4 = bitcast half %tmp3 to i16
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%tmp5 = insertelement <2 x i16> <i16 0, i16 undef>, i16 %tmp4, i32 1
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%tmp6 = bitcast i16* %arg to half*
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store half %tmp2, half* %tmp6, align 2
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%tmp7 = bitcast <2 x i16> %tmp to <2 x half>
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%tmp8 = extractelement <2 x half> %tmp7, i32 0
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br label %bb1
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}
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attributes #0 = { nounwind }
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@ -49,9 +49,9 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo(half %src0, half %src
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}
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
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; GFX9: v_mov_b32_e32 v3, 0
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; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2
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; GFX9-NEXT: v_mov_b32_e32 v0, v3
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; GFX9: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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; GFX9-NEXT: s_setpc_b64
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define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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@ -66,9 +66,9 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha
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}
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
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; GFX9: v_mov_b32_e32 v3, 0
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; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2
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; GFX9-NEXT: v_mov_b32_e32 v0, v3
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; GFX9: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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; GFX9-NEXT: s_setpc_b64
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define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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