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6482 Commits

Author SHA1 Message Date
Derek Pappas 7292969bf9
Nomi5 (#1726) 
* adding getOMComponents to ports

* fixing formatting

* created a new getOMPortMemoryRegions

* cosmetic
 2018-11-30 08:37:41 -08:00
Henry Cook 1ec033af35 tile: all tiles have notification nodes 2018-11-29 12:38:32 -08:00
Henry Cook 1f1b35b23b tile: tileControlAddr is now tile param named beuAddr 2018-11-29 12:32:15 -08:00
Henry Cook ef4c42bea2 tile: trace port exists unconditionally 2018-11-29 12:26:56 -08:00
Henry Cook 52bc980ed9 subsystem: BankedL2Params.coherenceManager returns Option[IntOutwardNode] 2018-11-29 12:20:52 -08:00
Henry Cook 12f45cb08c interrupts: add xbar factory 2018-11-29 12:15:02 -08:00
Wesley W. Terpstra 2303e93e57 Tiles: place at the top of the chip graph 2018-11-28 19:42:08 -08:00
Wesley W. Terpstra 16a94678aa AddressAdjuster: report which slaves have conflicting width 2018-11-28 19:41:14 -08:00
Wesley W. Terpstra b50b1959b5 AXI4ToTL: always select the error device with the largest transfer 2018-11-28 18:48:16 -08:00
Jack Koenig e03605a934
Bump firrtl (#1719) 
Major changes:
* Target (Named deprecated)
* RegisteredTransform
* Cats herded in emitted Verilog
* Bug fixes
 2018-11-28 16:25:37 -08:00
Sandeep Rajendran ab893da7c2
Merge pull request #1723 from freechipsproject/event_covers 
Fix event covers to eliminate dead covers
 2018-11-27 20:39:08 -08:00
Sandeep Rajendran c9c3712039 Fix event covers to eliminate dead covers 2018-11-27 15:48:49 -08:00
Henry Cook f026df71c9 tile: beu addr is rocekt tile param 2018-11-27 11:09:24 -08:00
Henry Cook ed9adcbcb5 tile: move BEU from rocket to tile 2018-11-27 11:04:53 -08:00
Andrew Waterman 3915e15833
Merge pull request #1712 from freechipsproject/priv-stuff 
Priv arch enhancements
 2018-11-26 17:00:58 -08:00
Andrew Waterman c3b2815de2 Remove legacy CSR names 2018-11-26 14:26:16 -08:00
Andrew Waterman c255988102 Add PAUSE hint 2018-11-26 13:20:07 -08:00
Andrew Waterman 29954c6ffe D$ optimization: don't drain store buffer if merge opportunity pending 2018-11-24 17:30:39 -08:00
Andrew Waterman bbde864bfa optionally expose tile-level cease signal 2018-11-24 17:30:34 -08:00
Andrew Waterman 2bfe9582de D$: add some more advisory signals to help pipeline scheduling 2018-11-24 17:30:34 -08:00
Wesley W. Terpstra e9dc7d0fc9
RationalIO: set directions so it works inside chisel3 aggregates (#1718) 2018-11-21 19:00:28 -10:00
Jack Koenig c582ed8b3f Fix non-determinism in TLMonitor generation (#1713) 
groupBy considered harmful
 2018-11-21 13:33:26 -10:00
Andrew Waterman daefbd0228 Add optional CFLUSH.D.L1 instruction 
This flushes the D$.  It is only meant for power-down and it is only
supported on systems without S-mode.
 2018-11-21 13:59:25 -08:00
Andrew Waterman a5dc8d378e Remove vestigial method RocketTile.findScratchpadFromICache 2018-11-21 13:59:25 -08:00
Andrew Waterman fc496819c7 Pass diplomatic RocketTile to RocketCore 2018-11-21 13:59:25 -08:00
Andrew Waterman e88774140c Add CEASE instruction 
After retiring this instruction, no further instructions will retire
until reset (including debugging).
 2018-11-21 13:59:25 -08:00
Andrew Waterman edb0e6c4dd Canonicalize names of mtval, stval, and satp 
We'll leave the old definitions for a short grace period.
 2018-11-21 13:59:25 -08:00
Andrew Waterman 988df864bf
Merge pull request #1652 from freechipsproject/debug-clock-gating 
Clock-gate the debug module using the dmactive signal
 2018-11-21 13:55:36 -08:00
Andrew Waterman 8a79e6f477 Clock-gate the debug module using the dmactive signal 2018-11-20 12:39:58 -08:00
Wesley W. Terpstra 089ad89e85
Merge pull request #1671 from freechipsproject/power-queues 
Power queues
 2018-11-20 09:16:03 -10:00
Wesley W. Terpstra 1899b6cf69 LanePositionedQueue: support 'pipe' mode as well 2018-11-19 23:52:40 -08:00
Wesley W. Terpstra fb89b337a7 MultiPortQueue: support also degenerate case (1 lane) 2018-11-19 23:51:55 -08:00
Wesley W. Terpstra 381be05dec ScatterGather: make it possible to insert pipeline stages 2018-11-19 23:51:44 -08:00
Wesley W. Terpstra 1e7d53cfbe LanePositionedQueue: adjust API to reveal total data and space available 
Necessary when a feed-forward multi-stage pipeline feeds a LPQ.
 2018-11-19 23:51:44 -08:00
Wesley W. Terpstra 7ab6c8e671 MultiPortQueue: decouple enq/deq/storage lanes 2018-11-19 23:51:44 -08:00
Wesley W. Terpstra 405da4b365 MultiPortQueue: allow dense and sparse sizes to differ 2018-11-19 23:51:44 -08:00
Wesley W. Terpstra edd4090aca Multi{Lane,Port}Queue: support flow 2018-11-19 23:51:44 -08:00
Wesley W. Terpstra 58ff2bfb22 LanePositionedQueue: support flow 2018-11-19 23:51:44 -08:00
Wesley W. Terpstra 181dacbc75 MultiPortQueue: weaken intra-port ready-valid coupling 2018-11-19 23:51:44 -08:00
Wesley W. Terpstra 164f4fad43 MultiPortQueue: refactor code to provide reusable half-adapters 2018-11-19 23:51:44 -08:00
Wesley W. Terpstra 7fa5e88223 ScatterGather: allow for direct control of the summands 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra 4d6620e8f6 MultiLaneQueue: fix comment 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra 1ab462e933 MultiLaneQueue: a Queue which can enqueue variable-sized transactions 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra 5744792f82 MultiPortQueue: document deviation from ready-valid 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra 2a46fbde33 MultiPortQueue: improve QoR a bit 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra 3be4620bdb MultiPortQueue: leverage scatter+gather and the LanePositionedQueue! 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra 708ee6c8ff LanePositionedQueue: add ECC support 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra ef2d8b6467 LanePositionedQueue: don't use the SRAM when flops suffice 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra c3cd16a2b0 HellaCache: document the "well-known" bug 2018-11-19 23:51:43 -08:00
Wesley W. Terpstra ad6224fb4f LanePositionedQueue: hook abstraction up to unit test configs 2018-11-19 23:51:43 -08:00