tile: tileControlAddr is now tile param named beuAddr
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ef4c42bea2
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@ -66,6 +66,7 @@ case class TraceGenParams(
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numGens: Int) extends GroundTestTileParams {
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def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p)
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val hartId = 0
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val beuAddr = None
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val blockerCtrlAddr = None
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val name = None
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}
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@ -28,6 +28,7 @@ trait TileParams {
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val dcache: Option[DCacheParams]
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val btb: Option[BTBParams]
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val hartId: Int
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val beuAddr: Option[BigInt]
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val blockerCtrlAddr: Option[BigInt]
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val name: Option[String]
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}
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@ -38,7 +38,6 @@ trait CoreParams {
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val nL2TLBEntries: Int
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val mtvecInit: Option[BigInt]
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val mtvecWritable: Boolean
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val tileControlAddr: Option[BigInt]
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def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs
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def instBytes: Int = instBits / 8
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@ -93,7 +92,7 @@ abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundl
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with HasCoreParameters
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class CoreInterrupts(implicit p: Parameters) extends TileInterrupts()(p) {
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val buserror = coreParams.tileControlAddr.map(a => Bool())
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val buserror = tileParams.beuAddr.map(a => Bool())
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}
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trait HasCoreIO extends HasTileParameters {
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@ -21,7 +21,7 @@ case class RocketTileParams(
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hcfOnUncorrectable: Boolean = false,
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name: Option[String] = Some("tile"),
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hartId: Int = 0,
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beuControlAddr: Option[BigInt] = None,
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beuAddr: Option[BigInt] = None,
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blockerCtrlAddr: Option[BigInt] = None,
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boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
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) extends TileParams {
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@ -47,7 +47,7 @@ class RocketTile(
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}
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dtim_adapter.foreach(lm => connectTLSlave(lm.node, xBytes))
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val bus_error_unit = tileParams.beuControlAddr map { a =>
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val bus_error_unit = rocketParams.beuAddr map { a =>
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val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
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intOutwardNode := beu.intNode
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connectTLSlave(beu.node, xBytes)
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@ -118,18 +118,19 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
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core.io.cease
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))
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outer.bus_error_unit.foreach { lm =>
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lm.module.io.errors.dcache := outer.dcache.module.io.errors
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lm.module.io.errors.icache := outer.frontend.module.io.errors
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}
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outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
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outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
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halt_and_catch_fire.foreach { _ := uncorrectable }
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outer.frontend.module.io.cpu <> core.io.imem
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outer.frontend.module.io.reset_vector := constants.reset_vector
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outer.frontend.module.io.hartid := constants.hartid
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outer.bus_error_unit.foreach { beu =>
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core.io.interrupts.buserror.get := beu.module.io.interrupt
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beu.module.io.errors.dcache := outer.dcache.module.io.errors
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beu.module.io.errors.icache := outer.frontend.module.io.errors
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}
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// Pass through various external constants and reports
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trace := core.io.trace
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core.io.hartid := constants.hartid
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