0f0798a374
Make rocket publish a single jar.
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This puts macros + hardfloat in a single jar instead of being published
as separate jars.
2019-03-12 20:41:52 -07:00
79e58d4faa
Bump hardfloat, clean up build. ( #1865 )
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Hardfloat used to require Chisel 2 for testing, which is only published
for Scala 2.11. Rocket uses Scala 2.12, which meant the build system
needed a workaround to make hardfloat use Scala 2.12 when being used as
a part of rocket.
Hardfloat's tests have been updated to use Chisel 3, so the workaround
is no longer needed. This commit bumps the hardfloat submodule and
cleans up build.sbt to use Scala 2.12 only and Makefrag to not use
++2.12.4.
2019-03-09 10:35:02 -08:00
2e5268f4a2
Merge pull request #1866 from freechipsproject/fix-cflush-line
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Further fix per-line cache flushing
2019-03-07 23:37:58 -08:00
1dd1cac14b
Further fix CFLUSH.D.L1 with rs1 != x0
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Don't engage release state machine when release is outstanding
Partially revert 3f962e9a3d
2019-03-06 18:34:37 -08:00
4c2c15e138
Merge pull request #1862 from freechipsproject/flush-line-fix
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For per-address cache flushing, don't evict same line twice
2019-03-05 14:29:01 -08:00
fbb9aae8a4
Fail misaligned PMP checks in M-mode, even if they don't apply
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This doesn't actually affect any correct M-mode software, but
is technically necessary for spec compliance.
2019-03-05 02:59:13 -08:00
cf9d8e11a2
Add flag for rocket to conditionally use maven deps ( #1835 )
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Conditionally depend on chisel
* By default, depend on subproject in directory "chisel3"
* If environment variable "ROCKET_USE_MAVEN" is defined, use maven dependency
2019-03-04 22:17:26 -06:00
3f962e9a3d
For per-address cache flushing, don't evict same line twice
2019-03-04 15:55:20 -08:00
44138e3417
adding rangefilter to the getOMMemoryRegions gating expression ( #1859 )
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* adding rangefilter to the getOMMemoryRegions gating expression
2019-03-01 21:48:04 -08:00
ac8cb040c8
Changing riscv-tools hash to the latest master ( #1858 )
2019-02-28 20:40:50 -08:00
0ba94f4f66
Merge pull request #1857 from freechipsproject/mmio-corrupt
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Permit execution past corrupt uncached D-responses
2019-02-27 14:15:55 -08:00
e356db51bc
Merge pull request #1852 from freechipsproject/omecc-fix
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Object model: Make OMECC an OMEnum type
2019-02-27 11:43:18 -08:00
642830db1b
Add new RegField apply function ( #1856 )
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* adding Option[RegFieldDesc]
2019-02-26 18:41:43 -08:00
4784c3f405
Permit execution past corrupt uncached D-responses
2019-02-26 15:16:01 -08:00
d2e96b7c6a
fix ( #1855 )
2019-02-23 19:16:16 -08:00
cf67a65d42
Merge pull request #1854 from freechipsproject/mimpid-parameter
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Make the mimpid CSR value a parameter
2019-02-23 18:46:47 -08:00
d1403b0a2e
D$: don't allow CFLUSH to retire until release acks are collected
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This isn't a bug fix, but will eventually help with powering off the cache.
2019-02-22 15:32:26 -08:00
8b79991c8f
Make the mimpid CSR value a parameter
2019-02-22 15:09:30 -08:00
bc5eeea38a
OM: Make OMECC an OMEnum type
2019-02-21 17:08:15 -08:00
d29c1ac9b6
Merge pull request #1849 from freechipsproject/fpu-clock-gate
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Move FPU load pipeline register into ungated clock domain
2019-02-20 17:04:54 -08:00
bb5cae70d8
Move FPU load pipeline register into ungated clock domain
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This avoids having to clock the FPU during MMIO loads, right up until
the load comes back.
2019-02-20 12:05:37 -08:00
a05728c4fa
Merge pull request #1846 from freechipsproject/frontend-clock-gate-improvement
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Increase the number of situations in which frontend can be clock gated
2019-02-16 19:43:55 -08:00
af5dbd5de0
Add external global interrupts ( #1845 )
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Add external global interrupts
2019-02-15 18:00:55 -08:00
c569908857
Increase the number of situations in which frontend can be clock gated
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The fetch queue needs to fill up, which currently is only possible with
certain code sequences. This PR makes the fetch queue flow control exact
rather than conservative, removing the software constraint.
2019-02-15 15:50:04 -08:00
105780efe8
fix ( #1844 )
2019-02-14 19:26:25 -08:00
a9be0e7334
Merge pull request #1843 from freechipsproject/bump-firrtl
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Bump firrtl
2019-02-14 18:21:20 -08:00
3f3aa35469
Bump firrtl
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Summary of changes:
* Async Reset Register support
* Minor improvements to constant propagation and code generation
* Minor performance improvements
* Add "mverilog" compiler with minimal optimizations
2019-02-14 15:17:07 -08:00
b7ff1b5dd3
Merge pull request #1842 from freechipsproject/clocked_core_monitors
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Extend CoreMonitorBundle with Clocked trait.
2019-02-13 19:30:07 -08:00
15b4354392
Extend CoreMonitorBundle with Clocked trait.
2019-02-13 11:22:28 -08:00
313cd1ff7e
Vivado bram fix ( #1838 )
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* testing fix to correctly generate brams in vivado
* added case of no maskpid
* fixed typo
2019-02-12 20:10:20 -08:00
c3e03be0f5
BusBlocker: add RegFieldDescs to the control port ( #1839 )
2019-02-12 20:08:06 -08:00
f924d1cff3
tile: add unifyManagers to BaseTile ( #1837 )
2019-02-12 20:07:34 -08:00
e6aaca28b7
OMISA user fix ( #1836 )
2019-02-12 16:27:33 -08:00
f58f8c96b2
axi4: add HasAXI4ControlRegMap ( #1833 )
2019-02-12 10:49:15 -08:00
91e8bab27d
Global om ( #1824 )
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* adding global storage of components not in the logical tree
2019-02-12 01:03:03 -08:00
53dc5d2b8b
Ports.scala: add comment re. capping test-harness MMIO to 4KB ( #1831 )
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-02-11 18:16:40 -08:00
3753ede1a6
DTM: Don't accept DMI response when busy ( #1829 )
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* Don't accept DMI response when DMI Busy error bit is set.
* DebugTransport code cleanup
2019-02-09 15:53:32 -08:00
75f8ab8240
Merge pull request #1830 from freechipsproject/cflush-addr
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Support CFLUSH.D.L1 rs1 address argument
2019-02-09 15:49:05 -08:00
4680989714
Support CFLUSH.D.L1 rs1 address argument
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When rs1 = x0, it flushes the whole cache.
When rs1 != x0, it flushes the line containing the address in rs1.
2019-02-08 23:57:58 -08:00
4c1292f96b
Check for write permissions on CFLUSH.D.L1 addresses
2019-02-08 23:57:34 -08:00
8eca7c49f9
Add per-line flush support to D$
2019-02-08 23:57:14 -08:00
e59b2844bc
Merge pull request #1820 from freechipsproject/fix-generator
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generator: support the no rocket tiles case
2019-02-08 10:31:17 -08:00
1565563285
Added ExportDisableDebug flag to expose optional disableDebug input ( #1823 )
2019-02-08 09:34:58 -07:00
6f4f14b86c
Merge pull request #1821 from freechipsproject/l2-tlb-qor
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Get L2 TLB parity check off the critical path
2019-02-08 00:56:04 -08:00
441d7f6862
Avoid import from chisel3.core ( #1827 )
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Close #1817
2019-02-07 18:15:16 -08:00
c0333f8de6
Add utility groupByIntoSeq and use instead of groupBy for determinism ( #1825 )
2019-02-07 14:10:26 -08:00
e831ca3151
name fix for TIM's ( #1822 )
2019-02-06 16:12:59 -08:00
8ce3887c78
Debug: Added halt groups. ( #1744 )
2019-02-06 13:38:35 -07:00
2727c8e73b
Get L2 TLB parity check off the critical path
2019-02-05 19:09:35 -08:00
5a84844360
divminlatency = 2 ( #1819 )
2019-02-05 13:08:18 -08:00
Paul Rigge