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hqjenny-rocket-chip
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D$ optimization: don't drain store buffer if merge opportunity pending

This commit is contained in:
Andrew Waterman 2018-11-19 17:29:20 -08:00
parent bbde864bfa
commit 29954c6ffe
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/DCache.scala
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@ -354,8 +354,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val pstore1_merge_likely = s2_valid && s2_write && s2_store_merge
val pstore1_merge = s2_store_valid && s2_store_merge
val pstore2_valid = Reg(Bool())
val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits))
val pstore_drain_on_miss = releaseInFlight
val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard)
val pstore_drain_on_miss = releaseInFlight || RegNext(io.cpu.s2_nack)
val pstore1_held = Reg(Bool())
val pstore1_valid_likely = s2_valid && s2_write || pstore1_held
val pstore1_valid_pre_kill = s2_store_valid_pre_kill || pstore1_held