MultiPortQueue: document deviation from ready-valid

2018-10-18 11:42:52 -07:00 · 2018-10-18 11:42:52 -07:00 · 5744792f82
parent 2a46fbde33
commit 5744792f82
1 changed files with 1 additions and 0 deletions
--- a/src/main/scala/util/MultiPortQueue.scala
+++ b/src/main/scala/util/MultiPortQueue.scala
@ -8,6 +8,7 @@ import chisel3.util._
 class MultiPortQueue[T <: Data](gen: T, val lanes: Int, val rows: Int, storage: LanePositionedQueue = FloppedLanePositionedQueue) extends Module {
  val io = IO(new Bundle {
    val enq = Flipped(Vec(lanes, Decoupled(gen)))
+    // NOTE: deq.{valid,bits} depend on deq.ready; if this is a problem, add a flow queue.
    val deq = Vec(lanes, Decoupled(gen))
  })