a2d25a1776
Add a PSDTestModeBroadcastKey Config Parameter ( #1818 )
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* PSDTestMode: Add a Config knob for the PSD Bundle Broadcast
* PSDTestModeBroadcastKey: update field type
2019-02-05 13:00:10 -08:00
e22df2ff91
generator: support the no rocket-chip case
2019-02-05 03:32:10 -08:00
f52950325b
Merge pull request #1812 from freechipsproject/add_cover_points_pmp
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Adding cover points for pmp permission, and access
2019-02-03 16:00:56 -08:00
f923a082b2
Merge pull request #1815 from freechipsproject/correct_the_csr_cover_point
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Removing the CSR.R as a measure of accessing the csr
2019-02-03 16:00:40 -08:00
0dc7ede275
Removing the CSR.R as a measure of accessing the csr
2019-02-01 16:30:51 -08:00
178a93b587
Indenting for the loop
2019-02-01 16:21:58 -08:00
182178d943
Bump verilator to v4.008 ( #1762 )
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* Bump verilator to 4.008
* update verilator opt, which more user friendly
* Update thread number for unittest design for travis test
2019-02-01 14:36:49 -08:00
f5ce1543f9
unicode fix ( #1813 )
2019-01-31 21:56:46 -08:00
cf048eb481
Merge pull request #1786 from freechipsproject/qor
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Minor QoR improvements
2019-01-31 19:27:13 -08:00
2b64cbcc14
correcting the string passing
2019-01-31 15:12:04 -08:00
53b88546e3
AsyncReset: iverilog requires named initial block with `RANDOMIZE ( #1807 )
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When simulating with iverilog, we get an error message for the
assignment to _RAND in the module's initial block:
"Variable declaration in unnamed block requires SystemVerilog."
Provide a name (":B0") for the initial block, which should be a
syntac no-op for already supported simulators, and allow also
running simulations under iverilog.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-01-31 14:44:29 -08:00
346ba318d1
adding the missing library
2019-01-31 14:26:57 -08:00
b704835189
changes made as suggested by review
2019-01-31 13:59:32 -08:00
de26108e13
adding cover points to check if each of pmp access is set
2019-01-31 13:13:27 -08:00
5b761a12cd
Fix faulty assertion in D$
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derp
2019-01-31 12:06:42 -08:00
007229f74b
Fix ECC/MMIO interaction from bff1be53b1f226e22a54b8c2921693fd55ab1ae0
2019-01-31 12:06:42 -08:00
228498ded6
Make OptimizationBarrier work in synthesis; use it
2019-01-31 12:06:42 -08:00
58db99deb2
Replicate D$ ECC encoder to remove arbiter -> ECC critical path
2019-01-31 12:06:42 -08:00
d5faae05a1
Reduce critical path through D$ hazard checks
2019-01-31 12:06:42 -08:00
3ba15f82c4
Reduce delay between ECC and s2_nack/resp.valid
2019-01-31 12:06:42 -08:00
8ef996aff0
Improve D$ ECC QoR by removing post-ECC word mux
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It is instead merged into the way mux.
2019-01-31 12:06:42 -08:00
e1b4f5ad37
Replace toBool(s) with asBool(s) ( #1809 )
2019-01-30 18:44:51 -08:00
84252d2445
Om scala plic fix1 ( #1800 )
2019-01-30 12:03:29 -08:00
aba5773441
Merge pull request #1806 from freechipsproject/pmp-reset
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Encapsulate PMP reset
2019-01-29 20:32:53 -08:00
c3bdbd8ada
add docname ( #1802 )
2019-01-29 11:31:33 -08:00
9a0f4df75a
Merge pull request #1808 from freechipsproject/bump_riscv_tools_for_spike_fix
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Bumping riscv-tools
2019-01-29 10:00:07 -08:00
3e7beb866d
bumping riscv-tools
2019-01-28 17:44:20 -08:00
d859a1c048
Encapsulate PMP reset
2019-01-28 13:42:37 -08:00
e86a4df663
Support delegation of misaligned ld/st and illegal instruction traps ( #1799 )
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This facilitates moving emulation code out of the M-mode trusted codebase.
2019-01-25 11:15:54 -08:00
b4f732fc9f
subsystem: add a fragmenter to tile slave port bus blocker control ( #1801 )
2019-01-24 19:19:23 -08:00
1d947b6653
* Added HasCoreMonitor trait to HasTiles trait ( #1797 )
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* Moved CoreMonitorBundle class to util package
2019-01-22 14:22:26 -08:00
8eec2204cf
Debug interface ( #1794 )
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* adding cjtag
2019-01-21 16:41:36 -08:00
c15bfe49d5
remove require from ECCParams ( #1792 )
2019-01-21 10:08:44 -08:00
b9b95f493a
adding missing type ( #1791 )
2019-01-18 23:33:12 -08:00
fb5ac38480
added per channel BufferParams case classes for TL, AXI4 ( #1787 )
2019-01-18 11:08:07 -08:00
4b37841872
Relax assertion in Debug.scala, allow dmactive to be used to exit from busy state in DM ( #1782 )
2019-01-17 10:19:13 -08:00
68380eb9c3
Merge pull request #1784 from freechipsproject/seip-clock-gate
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Respect SEIP during WFI clock gate
2019-01-17 10:02:08 -08:00
508dd91184
Merge pull request #1783 from freechipsproject/fuzzing-plusarg
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rename ahb_fuzzing plusarg
2019-01-17 09:33:44 -08:00
d79cd12252
Avoid excess tag write after flush
2019-01-17 02:34:27 -08:00
976a8aa163
Respect SEIP during WFI clock gate
2019-01-16 22:47:34 -08:00
c1c3f7356c
rename ahb_fuzzing plusarg
2019-01-16 17:21:22 -08:00
e0c622cc50
Merge pull request #1781 from freechipsproject/fuzzing-plusarg
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Add plusarg option to disable fuzzing
2019-01-16 15:23:54 -08:00
e9aa5c5123
adding om registers ( #1773 )
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* adding registers to the OM
2019-01-16 11:17:20 -08:00
0b57334e18
Add plusarg option to disable fuzzing
2019-01-16 10:18:53 -08:00
772a8a475d
AXI4Fragmenter: splitting up bursts impacts the inflight transactions ( #1780 )
2019-01-15 20:05:50 -08:00
6bbcf622a3
Merge pull request #1776 from freechipsproject/qor
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Minor QoR improvements
2019-01-15 16:59:47 -08:00
79c3d9880a
Fix typo in fragmented-superpage handling code
2019-01-15 14:46:33 -08:00
c76bb44e32
Move getomcomponents1 ( #1772 )
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* changing where getOMComponents is called in the flow
2019-01-15 11:11:47 -08:00
a9a90afd6b
Minor D$ QoR improvement
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s2_xcpt doesn't need to drive so many things.
2019-01-11 22:27:41 -08:00
ad61beed8a
Merge pull request #1775 from freechipsproject/trace-node-name
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Trace: suggestName trace node
2019-01-11 17:47:27 -08:00
Megan Wachs