Bea Healy 27fdf5525c [Arc] Fix arc inliner deleting arcs that still have calls (#8510)		2025-05-23 10:09:07 +01:00
..
Export	[Arc] Add arc.final op (#7700)	2024-10-14 09:49:24 -07:00
Reduction	[HW] Add reduction patterns to trim port list of top-level module (#7587)	2024-09-16 19:47:26 +01:00
add-taps.mlir	[Arc] Remove hw.wire once it is tapped (#6372)	2023-11-02 18:19:48 +01:00
allocate-state.mlir	[Arc] Remove obsolete arc.clock_tree and arc.passthrough ops (#7704)	2024-10-28 15:01:34 -07:00
arc-canonicalizer.mlir	[Arc] Make the canonicalizer shuffle the input vector elements before merging (#7394)	2024-08-03 22:51:13 -07:00
basic-errors.mlir	[Arc] Add arc.final op (#7700)	2024-10-14 09:49:24 -07:00
basic.mlir	[Arc][NFC] Tweak arc op docs and add missing test	2024-10-13 18:24:37 -07:00
canonicalizers.mlir	[Arc] Fix folding of initialized StateOp (#7653)	2024-10-02 16:45:58 +02:00
dedup.mlir	[Arc] Use CallOp instead of latency 0 StateOp (#6560)	2024-01-11 13:48:51 +01:00
find-initial-vectors.mlir	[Arc] Add prefix to FindInitialVectors pass option	2024-05-27 15:40:27 -07:00
infer-memories-names.mlir	[Arc] Add option to observe registers and memories (#6477)	2023-12-02 09:22:23 -08:00
infer-memories.mlir	[Arc] StateOp: latency instead of lat in assembly format (#6562)	2024-01-12 07:54:39 +01:00
infer-state-properties.mlir	[Arc] StateOp: latency instead of lat in assembly format (#6562)	2024-01-12 07:54:39 +01:00
inline-arcs.mlir	[Arc] Fix arc inliner deleting arcs that still have calls (#8510)	2025-05-23 10:09:07 +01:00
isolate-clocks-error.mlir	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
isolate-clocks.mlir	[Arc] StateOp: latency instead of lat in assembly format (#6562)	2024-01-12 07:54:39 +01:00
latency-retiming.mlir	[Arc] StateOp: latency instead of lat in assembly format (#6562)	2024-01-12 07:54:39 +01:00
lower-arcs-to-funcs.mlir	[Arc] Use CallOp instead of latency 0 StateOp (#6560)	2024-01-11 13:48:51 +01:00
lower-clocks-to-funcs-errors.mlir	[Arc] Remove obsolete arc.clock_tree and arc.passthrough ops (#7704)	2024-10-28 15:01:34 -07:00
lower-clocks-to-funcs.mlir	[Arc] Remove obsolete arc.clock_tree and arc.passthrough ops (#7704)	2024-10-28 15:01:34 -07:00
lower-lut.mlir	[Arc] Add lookup table op and lowering pass (#4726)	2023-03-15 21:44:47 -07:00
lower-sim.mlir	[NFC] LLVM bump	2024-05-06 17:26:26 -05:00
lower-state-errors.mlir	[Arc] Don't let LowerState delete instantiated external modules (#8470)	2025-05-08 17:44:56 +01:00
lower-state.mlir	[Arc] Improve LowerState to never produce read-after-write conflicts (#7703)	2024-10-28 14:57:03 -07:00
lower-vectorizations-boundary.mlir	[NFC] LLVM bump	2023-10-03 09:24:06 -05:00
lower-vectorizations-full.mlir	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
lower-vectorizations-inline-body.mlir	[NFC] LLVM bump	2023-10-03 09:24:06 -05:00
lower-verif-simulations-error.mlir	[Arcilator] Allow running verif.simulation ops (#8233)	2025-02-18 10:50:11 -08:00
lower-verif-simulations.mlir	[Verif] Change simulation exit code to success boolean (#8253)	2025-02-19 16:03:45 -08:00
make-tables.mlir	[Arc] Add lookup table generation pass (#4682)	2023-03-15 21:41:12 -07:00
merge-ifs.mlir	[Arc] Add dominance-aware pass to sink ops and merge scf.if ops (#7702)	2024-10-15 11:38:29 -07:00
mux-to-control-flow.mlir	[Arc] Add MuxToControlFlow pass	2023-03-28 14:37:48 -07:00
sim-errors.mlir	[arcilator] Introduce simulation orchestration subdialect (#6695)	2024-03-02 11:34:02 +00:00
simplify-variadic-ops.mlir	[Arc] Add variadic op simplification pass (#4724)	2023-03-15 21:43:09 -07:00
split-funcs-errors.mlir	[Arc] Add SplitFuncsPass (#7027)	2024-05-15 18:03:38 +01:00
split-funcs.mlir	[Arc] Add SplitFuncsPass (#7027)	2024-05-15 18:03:38 +01:00
split-loops-errors.mlir	[Arc] Use CallOp instead of latency 0 StateOp (#6560)	2024-01-11 13:48:51 +01:00
split-loops.mlir	[Arc] Fix segfault in SplitLoops (#6928)	2024-04-18 09:24:01 +02:00
strip-sv.mlir	[SV] Use a symbol in macro identifiers (#6777)	2024-03-04 13:12:27 +02:00