Fabian Schuiki 24522338f2 [Arc] Add arc.final op (#7700) ... Add the `arc.final` op to complement the existing `arc.initial`. The body of `arc.final` is executed after the last time step, when the simulation is shut down. This corresponds to SystemVerilog's `final` procedure, and can also be used to report statistics about which `cover` statements were hit, or to check if an `eventually` property has been satisfied. The `arc.final` op is extracted into a `*_final` function. The contract with the user is that the `*_final` function must be called exactly once after the last call to `*_eval`. The simulation lifetime now looks like this: ``` design_initial() design_eval() design_eval() design_eval() ... design_eval() design_final() ``` The `arc.sim.instantiate` op inserts a corresponding call to `*_final` when lowering to LLVM.		2024-10-14 09:49:24 -07:00
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info-gathering-errors.mlir	[arcilator] Introduce simulation orchestration subdialect (#6695)	2024-03-02 11:34:02 +00:00
serialize-state-info.mlir	[Arc] Add arc.final op (#7700)	2024-10-14 09:49:24 -07:00