mirror of https://github.com/llvm/circt.git
94 lines
6.9 KiB
MLIR
94 lines
6.9 KiB
MLIR
// RUN: circt-opt %s --arc-infer-memories=tap-ports=0 | FileCheck %s
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hw.generator.schema @FIRRTLMem, "FIRRTL_Memory", ["depth", "numReadPorts", "numWritePorts", "numReadWritePorts", "readLatency", "writeLatency", "width", "maskGran", "readUnderWrite", "writeUnderWrite", "writeClockIDs"]
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// CHECK-LABEL: hw.module @TestWOMemory(
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hw.module @TestWOMemory(in %clock: !seq.clock, in %addr: i10, in %enable: i1, in %data: i8) {
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// CHECK-NOT: hw.instance
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// CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8, i10> {name = "foo"}
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// CHECK-NEXT: arc.memory_write_port [[FOO]], @mem_write{{.*}}(%addr, %data, %enable) clock %clock enable latency 1 : <1024 x i8, i10>, i10, i8, i1
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// CHECK-NEXT: hw.output
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hw.instance "foo" @WOMemory(W0_addr: %addr: i10, W0_en: %enable: i1, W0_clk: %clock: !seq.clock, W0_data: %data: i8) -> ()
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}
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// CHECK-NEXT: }
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// CHECK-NOT: hw.module.generated @WOMemory, @FIRRTLMem
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hw.module.generated @WOMemory, @FIRRTLMem(in %W0_addr: i10, in %W0_en: i1, in %W0_clk: !seq.clock, in %W0_data: i8) attributes {depth = 1024 : i64, maskGran = 8 : ui32, numReadPorts = 0 : ui32, numReadWritePorts = 0 : ui32, numWritePorts = 1 : ui32, readLatency = 1 : ui32, readUnderWrite = 0 : ui32, width = 8 : ui32, writeClockIDs = [], writeLatency = 1 : ui32, writeUnderWrite = 1 : i32}
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// CHECK-LABEL: hw.module @TestWOMemoryWithMask(
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hw.module @TestWOMemoryWithMask(in %clock: !seq.clock, in %addr: i10, in %enable: i1, in %data: i16, in %mask: i2) {
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// CHECK-NOT: hw.instance
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// CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i16, i10> {name = "foo"}
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// CHECK-NEXT: [[MASK_BIT0:%.+]] = comb.extract %mask from 0 : (i2) -> i1
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// CHECK-NEXT: [[MASK_BYTE0:%.+]] = comb.replicate [[MASK_BIT0]] : (i1) -> i8
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// CHECK-NEXT: [[MASK_BIT1:%.+]] = comb.extract %mask from 1 : (i2) -> i1
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// CHECK-NEXT: [[MASK_BYTE1:%.+]] = comb.replicate [[MASK_BIT1]] : (i1) -> i8
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// CHECK-NEXT: [[MASK:%.+]] = comb.concat [[MASK_BYTE1]], [[MASK_BYTE0]]
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// CHECK-NEXT: arc.memory_write_port [[FOO]], @mem_write{{.*}}(%addr, %data, %enable, [[MASK]]) clock %clock enable mask latency 1 : <1024 x i16, i10>, i10, i16, i1, i16
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// CHECK-NEXT: hw.output
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hw.instance "foo" @WOMemoryWithMask(W0_addr: %addr: i10, W0_en: %enable: i1, W0_clk: %clock: !seq.clock, W0_data: %data: i16, W0_mask: %mask: i2) -> ()
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}
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// CHECK-NEXT: }
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// CHECK-NOT: hw.module.generated @WOMemoryWithMask, @FIRRTLMem
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hw.module.generated @WOMemoryWithMask, @FIRRTLMem(in %W0_addr: i10, in %W0_en: i1, in %W0_clk: !seq.clock, in %W0_data: i16, in %W0_mask: i2) attributes {depth = 1024 : i64, maskGran = 8 : ui32, numReadPorts = 0 : ui32, numReadWritePorts = 0 : ui32, numWritePorts = 1 : ui32, readLatency = 1 : ui32, readUnderWrite = 0 : ui32, width = 16 : ui32, writeClockIDs = [], writeLatency = 1 : ui32, writeUnderWrite = 1 : i32}
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// CHECK-LABEL: hw.module @TestROMemory(
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hw.module @TestROMemory(in %clock: !seq.clock, in %addr: i10, in %enable: i1, out data: i8) {
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// CHECK-NOT: hw.instance
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// CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8, i10> {name = "foo"}
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// CHECK-NEXT: [[RDATA:%.+]] = arc.memory_read_port [[FOO]][%addr] : <1024 x i8, i10>
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// CHECK-NEXT: [[ZERO:%.+]] = hw.constant 0 : i8
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// CHECK-NEXT: [[MUX:%.+]] = comb.mux %enable, [[RDATA]], [[ZERO]] : i8
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// CHECK-NEXT: hw.output [[MUX]]
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%0 = hw.instance "foo" @ROMemory(R0_addr: %addr: i10, R0_en: %enable: i1, R0_clk: %clock: !seq.clock) -> (R0_data: i8)
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hw.output %0 : i8
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}
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// CHECK-NEXT: }
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// CHECK-NOT: hw.module.generated @ROMemory, @FIRRTLMem
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hw.module.generated @ROMemory, @FIRRTLMem(in %R0_addr: i10, in %R0_en: i1, in %R0_clk: !seq.clock, out R0_data: i8) attributes {depth = 1024 : i64, maskGran = 8 : ui32, numReadPorts = 1 : ui32, numReadWritePorts = 0 : ui32, numWritePorts = 0 : ui32, readLatency = 0 : ui32, readUnderWrite = 0 : ui32, width = 8 : ui32, writeClockIDs = [], writeLatency = 1 : ui32, writeUnderWrite = 1 : i32}
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// CHECK-LABEL: hw.module @TestROMemoryWithLatency(
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hw.module @TestROMemoryWithLatency(in %clock: !seq.clock, in %addr: i10, in %enable: i1, out data: i8) {
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// CHECK-NOT: hw.instance
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// CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8, i10> {name = "foo"}
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// CHECK-NEXT: [[ADDR0:%.+]] = seq.compreg %addr, %clock
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// CHECK-NEXT: [[ADDR1:%.+]] = seq.compreg [[ADDR0]], %clock
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// CHECK-NEXT: [[ADDR2:%.+]] = seq.compreg [[ADDR1]], %clock
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// CHECK-NEXT: [[EN0:%.+]] = seq.compreg %enable, %clock
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// CHECK-NEXT: [[EN1:%.+]] = seq.compreg [[EN0]], %clock
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// CHECK-NEXT: [[EN2:%.+]] = seq.compreg [[EN1]], %clock
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// CHECK-NEXT: [[D0:%.+]] = arc.memory_read_port [[FOO]][[[ADDR2]]] : <1024 x i8, i10>
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// CHECK-NEXT: [[ZERO:%.+]] = hw.constant 0 : i8
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// CHECK-NEXT: [[D1:%.+]] = comb.mux [[EN2]], [[D0]], [[ZERO]] : i8
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// CHECK-NEXT: hw.output [[D1]]
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%0 = hw.instance "foo" @ROMemoryWithLatency(R0_addr: %addr: i10, R0_en: %enable: i1, R0_clk: %clock: !seq.clock) -> (R0_data: i8)
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hw.output %0 : i8
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}
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// CHECK-NEXT: }
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// CHECK-NOT: hw.module.generated @ROMemoryWithLatency, @FIRRTLMem
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hw.module.generated @ROMemoryWithLatency, @FIRRTLMem(in %R0_addr: i10, in %R0_en: i1, in %R0_clk: !seq.clock, out R0_data: i8) attributes {depth = 1024 : i64, maskGran = 8 : ui32, numReadPorts = 1 : ui32, numReadWritePorts = 0 : ui32, numWritePorts = 0 : ui32, readLatency = 3 : ui32, readUnderWrite = 0 : ui32, width = 8 : ui32, writeClockIDs = [], writeLatency = 1 : ui32, writeUnderWrite = 1 : i32}
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// CHECK-LABEL: hw.module @TestRWMemory(
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hw.module @TestRWMemory(in %clock: !seq.clock, in %addr: i10, in %enable: i1, in %wmode: i1, in %wdata: i8, out rdata: i8) {
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// CHECK-NOT: hw.instance
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// CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8, i10> {name = "foo"}
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// CHECK-NEXT: [[TRUE:%.+]] = hw.constant true
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// CHECK-NEXT: [[NOT_WMODE:%.+]] = comb.xor %wmode, [[TRUE]]
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// CHECK-NEXT: [[RENABLE:%.+]] = comb.and %enable, [[NOT_WMODE]]
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// CHECK-NEXT: [[RDATA:%.+]] = arc.memory_read_port [[FOO]][%addr] : <1024 x i8, i10>
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// CHECK-NEXT: [[ZERO:%.+]] = hw.constant 0 : i8
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// CHECK-NEXT: [[MUX:%.+]] = comb.mux [[RENABLE]], [[RDATA]], [[ZERO]] : i8
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// CHECK-NEXT: [[WENABLE:%.+]] = comb.and %enable, %wmode
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// CHECK-NEXT: arc.memory_write_port [[FOO]], @mem_write{{.*}}(%addr, %wdata, [[WENABLE]]) clock %clock enable latency 1 : <1024 x i8, i10>, i10, i8, i1
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// CHECK-NEXT: hw.output [[MUX]]
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%0 = hw.instance "foo" @RWMemory(RW0_addr: %addr: i10, RW0_en: %enable: i1, RW0_clk: %clock: !seq.clock, RW0_wmode: %wmode: i1, RW0_wdata: %wdata: i8) -> (RW0_rdata: i8)
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hw.output %0 : i8
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}
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// CHECK-NEXT: }
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// CHECK-NOT: hw.module.generated @RWMemory, @FIRRTLMem
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hw.module.generated @RWMemory, @FIRRTLMem(in %RW0_addr: i10, in %RW0_en: i1, in %RW0_clk: !seq.clock, in %RW0_wmode: i1, in %RW0_wdata: i8, out RW0_rdata: i8) attributes {depth = 1024 : i64, maskGran = 8 : ui32, numReadPorts = 0 : ui32, numReadWritePorts = 1 : ui32, numWritePorts = 0 : ui32, readLatency = 0 : ui32, readUnderWrite = 0 : ui32, width = 8 : ui32, writeClockIDs = [], writeLatency = 1 : ui32, writeUnderWrite = 1 : i32}
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