Andrew Young cb90e658ab [FIRRTL] Make `sym_name` an inherent attr for symbol ops ... Making this an inherent attribute means that it will be stored in the properties of the operation. Some module-like classes already had declared it as an input, but our older modules kinds did not.		2024-11-01 23:16:34 -07:00
..
AIG	[AIG] Add CutOp (#7743)	2024-10-28 19:40:56 +09:00
Arc	[Arc] Remove obsolete arc.clock_tree and arc.passthrough ops (#7704)	2024-10-28 15:01:34 -07:00
Calyx	Calyx Binary Floating Point AddF Operator (#7089)	2024-10-31 17:41:21 -04:00
Comb	[CombFolds] Preserve two-state attribute in `narrowOperationWidth` (#7712)	2024-10-17 21:54:45 +02:00
DC	[NFC] Fix missing eof newline.	2024-08-15 15:09:33 -05:00
Debug	[Debug] Add scope op (#6454)	2023-12-08 09:38:46 -08:00
ESI	[ESI] Promote and generalize 'channel assignments' (#7715)	2024-10-18 02:18:14 -07:00
Emit	[Emit] Organize output files using the `emit` dialect (#6727)	2024-02-24 10:09:00 +02:00
FIRRTL	[FIRRTL] Make `sym_name` an inherent attr for symbol ops	2024-11-01 23:16:34 -07:00
FSM	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
HW	[HW][Seq] Allow typed attr to be an element of aggregate_constant and make seq.const_clock typed attr (#7718)	2024-10-22 15:53:10 +09:00
HWArith	[HWArith] Make `hwarith.icmp` result an `i1` (#7413)	2024-08-09 22:24:32 +02:00
Handshake	[NFC] Fix missing eof newline.	2024-08-15 15:09:33 -05:00
Ibis	[Ibis] Don't include design name in namespace in IbisContainersToHW (#7425)	2024-08-06 17:34:41 +02:00
Interop	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
LLHD	[LLHD][HW] Implement SROA interfaces (#7672)	2024-10-07 19:46:31 +01:00
LTL	[LTL] Canonicalize ltl.and to comb.and for i1 properties (#7759)	2024-11-01 09:11:00 -07:00
LoopSchedule	bump llvm submodule to tip of main (103fa3250c46) (#6589)	2024-01-19 09:45:35 -06:00
MSFT	[MSFT] Remove ChannelOp	2024-02-08 17:32:55 +00:00
Moore	[ImportVerilog] Add support for $clog2 (#7645)	2024-09-27 18:40:54 -07:00
OM	[OM] Add ClassOp region verifier	2024-10-28 16:39:10 -04:00
Pipeline	[Pipeline] Remove `Pure` trait from Pipeline operations (#6888)	2024-04-03 11:44:09 +02:00
SMT	[SMT] Minor width related fixes for BitVectorAttr (#6900)	2024-04-05 14:51:12 +02:00
SSP	[SSP] Add pass to roundtrip via the scheduling infra. (#4373)	2022-11-30 16:19:58 +13:00
SV	[SV] Add MacroRefOp to represet macro statement (#7607)	2024-09-25 17:29:57 +09:00
Seq	[HW][Seq] Allow typed attr to be an element of aggregate_constant and make seq.const_clock typed attr (#7718)	2024-10-22 15:53:10 +09:00
Sim	[Arc][Sim] Lower Sim DPI func to func.func and support dpi call in Arc (#7386)	2024-08-07 13:51:14 +09:00
SystemC	LLVM Bump (#6322)	2023-10-20 09:53:39 -07:00
Verif	[Verif] Adjust contract ops to match documentation (#7745)	2024-10-28 15:24:03 -07:00