Fabian Schuiki 9e79c341e5 [Verif] Change simulation exit code to success boolean (#8253) ... After some discussions on `verif.simulation`, the consensus seems to be that an arbitrary integer exit code that has no guarantee of being preserved properly by simulators, besides the zero vs non-zero distinction, is virtually useless in practice. Instead, simulations can be made simpler by generating a simple `i1` success result indicating whether the test passed or failed. Simulators can then map this to an appropriate exit code. The operating system's potential truncation of exit codes to fewer bits (e.g. 7 or 8 bits on Linux) is no longer an issue.		2025-02-19 16:03:45 -08:00
..
AIG	[AIG] Add CutOp (#7743)	2024-10-28 19:40:56 +09:00
Arc	[Verif] Change simulation exit code to success boolean (#8253)	2025-02-19 16:03:45 -08:00
Calyx	[Calyx] Canonicalize SCF IndexSwitch after AffineParallelUnroll (#8249)	2025-02-18 12:04:25 -05:00
Comb	[Comb] Don't try to canonicalize muxes indefinitely (#8023)	2025-01-01 22:01:42 +01:00
DC	[DC] Add + re-enable canonicalization patterns (#7952)	2024-12-09 19:01:27 +01:00
Debug	[Debug] Add scope op (#6454)	2023-12-08 09:38:46 -08:00
ESI	[ESI Runtime] Pluggable channel engines (#8167)	2025-02-03 16:52:39 -08:00
Emit	Add passes to strip OM and Emit dialect ops (#8121)	2025-01-27 13:56:52 -08:00
FIRRTL	[FIRRTL] Add optional yaml parameter to view intrinsic, op (#8203)	2025-02-07 13:51:07 -06:00
FSM	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
HW	[HW] Add array_concat of one element folder (#8181)	2025-02-03 18:01:47 +00:00
HWArith	[HWArith] Make `hwarith.icmp` result an `i1` (#7413)	2024-08-09 22:24:32 +02:00
Handshake	[Handshake] Adding func instance op for integration (#7812)	2024-11-15 12:00:40 -08:00
Interop	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
Kanagawa	[Kanagawa] Remove `%this` (#8097)	2025-01-21 09:38:54 +01:00
LLHD	[LLHD] Add canonicalizer for ProcessOp (#8221)	2025-02-11 20:53:05 +00:00
LTL	[LTL] Canonicalize ltl.and to comb.and for i1 properties (#7759)	2024-11-01 09:11:00 -07:00
LoopSchedule	bump llvm submodule to tip of main (103fa3250c46) (#6589)	2024-01-19 09:45:35 -06:00
MSFT	[MSFT] Remove ChannelOp	2024-02-08 17:32:55 +00:00
Moore	[ImportVerilog] Fix bit slicing into variables declared with offset (#8190)	2025-02-06 09:07:04 +00:00
OM	Add passes to strip OM and Emit dialect ops (#8121)	2025-01-27 13:56:52 -08:00
Pipeline	[Pipeline] Make `reset` signal optional (#8104)	2025-01-23 14:15:50 +01:00
RTG	[PyRTG] Support bags (#8236)	2025-02-19 13:42:12 +00:00
RTGTest/IR	[RTG] Custom assembly format for 'rtg.test' operation (#8188)	2025-02-19 11:27:58 +00:00
SMT	[SMT] Add bv2int op (#8049)	2025-01-10 13:30:34 +00:00
SSP	[SSP] Add pass to roundtrip via the scheduling infra. (#4373)	2022-11-30 16:19:58 +13:00
SV	[HW] ExportHier: do not include bound in modules (#7915)	2024-11-27 18:00:34 -08:00
Seq	[Seq] Copy fragments in HWMemSimImpl	2025-02-01 22:11:06 -05:00
Sim	[Arc][Sim] Lower Sim DPI func to func.func and support dpi call in Arc (#7386)	2024-08-07 13:51:14 +09:00
SystemC	LLVM Bump (#6322)	2023-10-20 09:53:39 -07:00
Verif	[Verif] Change simulation exit code to success boolean (#8253)	2025-02-19 16:03:45 -08:00