Reduce delay between ECC and s2_nack/resp.valid
This commit is contained in:
Andrew Waterman
parent
8ef996aff0
commit
3ba15f82c4
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@ -162,6 +162,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val s1_waw_hazard = Wire(Bool())
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val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: Nil = Enum(UInt(), 8)
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val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush
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val flushed = Reg(init=Bool(true))
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val cached_grant_wait = Reg(init=Bool(false))
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val release_ack_wait = Reg(init=Bool(false))
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val can_acquire_before_release = !release_ack_wait && release_queue_empty
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@ -301,9 +303,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR
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val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt
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val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt
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val s2_valid_hit_pre_data_ecc = s2_valid_masked && s2_readwrite && !s2_meta_error && s2_hit
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val s2_valid_data_error = s2_valid_hit_pre_data_ecc && s2_data_error && can_acquire_before_release
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val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error && (!s2_waw_hazard || s2_store_merge)
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val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_masked && s2_readwrite && !s2_meta_error && s2_hit
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val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard || s2_store_merge)
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val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error && can_acquire_before_release
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val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error
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val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit && can_acquire_before_release
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val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR
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dontTouch(s2_valid_cached_miss)
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@ -319,8 +322,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH)
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dontTouch(s2_victim_dirty)
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val s2_update_meta = s2_hit_state =/= s2_new_hit_state
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io.cpu.s2_nack := s2_valid_no_xcpt && !s2_valid_hit && !(s2_valid_uncached_pending && tl_out_a.ready)
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when (io.cpu.s2_nack || (s2_valid_hit && s2_update_meta)) { s1_nack := true }
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io.cpu.s2_nack := s2_valid_no_xcpt && !(s2_valid_uncached_pending && tl_out_a.ready || supports_flush && s2_req.cmd === M_FLUSH_ALL && flushed) && !s2_valid_hit
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when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true }
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// tag updates on ECC errors
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val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected)
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@ -336,7 +339,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// tag updates on hit
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metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc && s2_update_meta
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metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta
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metaArb.io.in(2).bits.write := !s2_data_error && !io.cpu.s2_kill
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metaArb.io.in(2).bits.way_en := s2_victim_way
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metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB)
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@ -363,7 +366,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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// don't perform data correction if it might clobber a recent store
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val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid) && Bool(usingDataScratchpad)
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// pending store buffer
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val s2_valid_correct = s2_valid_hit_pre_data_ecc && s2_correct && !io.cpu.s2_kill
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val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill
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def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail
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def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill
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val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write)
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@ -380,7 +383,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val pstore_drain_on_miss = releaseInFlight || RegNext(io.cpu.s2_nack)
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val pstore1_held = Reg(Bool())
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val pstore1_valid_likely = s2_valid && s2_write || pstore1_held
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def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && (!s2_waw_hazard || s2_store_merge) && s2_write && !s2_sc_fail && !s2_kill || pstore1_held
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def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill || pstore1_held
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val pstore1_valid = s2_store_valid || pstore1_held
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any_pstore_valid := pstore1_held || pstore2_valid
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val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw)
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@ -708,7 +711,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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when (metaArb.io.in(4).fire()) { release_state := s_ready }
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// cached response
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io.cpu.resp.valid := s2_valid_hit
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io.cpu.resp.bits <> s2_req
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io.cpu.resp.bits.has_data := s2_read
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io.cpu.resp.bits.replay := false
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@ -735,16 +737,16 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// uncached response
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io.cpu.replay_next := tl_out.d.fire() && grantIsUncachedData
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val doUncachedResp = Reg(next = io.cpu.replay_next)
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val s2_uncached_data_word = {
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val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
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val words = tl_out.d.bits.data.grouped(wordBits)
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RegEnable(words(word_idx), io.cpu.replay_next)
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}
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val doUncachedResp = Reg(next = io.cpu.replay_next)
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io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc || doUncachedResp) && !s2_data_error
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io.cpu.replay_next := tl_out.d.fire() && grantIsUncachedData
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when (doUncachedResp) {
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assert(!s2_valid_hit)
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io.cpu.resp.valid := true
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io.cpu.resp.bits.replay := true
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io.cpu.resp.bits.addr := s2_uncached_resp_addr
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}
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@ -779,7 +781,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val resetting = RegInit(false.B)
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if (!usingDataScratchpad)
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when (RegNext(reset)) { resetting := true }
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val flushed = Reg(init=Bool(true))
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val flushing = Reg(init=Bool(false))
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val flushCounter = Reg(init=UInt(nSets * (nWays-1), log2Ceil(nSets * nWays)))
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val flushCounterNext = flushCounter +& 1
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@ -796,10 +797,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data
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// Only flush D$ on FENCE.I if some cached executable regions are untracked.
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val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush
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if (supports_flush) {
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when (s2_valid_masked && s2_req.cmd === M_FLUSH_ALL) {
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io.cpu.s2_nack := !flushed
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when (!flushed) {
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flushing := !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR
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}
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