Commit Graph

29 Commits

Author SHA1 Message Date
Jenny Huang 7c0a7f7177 Add dprv connection for new Chipyard HellaCacheIO 2023-06-05 22:47:02 -07:00
Jenny Huang 3887cac15c Add logging info for sw wrapper 2023-06-01 14:24:44 -07:00
James Shi 31bcb9f64c working version 2023-04-03 18:37:48 -07:00
James Shi ae68d83f45 new fixes 2023-03-27 18:43:28 -07:00
James Shi 9edcc92d2f change path in config 2023-03-26 22:20:04 -07:00
James Shi 20ba20161d fixing some errors 2023-03-26 22:11:36 -07:00
lelzeiny 676b5f6f03 Previous debugging changes 2023-03-06 18:22:13 -08:00
lelzeiny 43fcb6339e Merging with current changes 2023-03-06 17:21:47 -08:00
James Shi b2b2f8e584 Initial fixes to generating build.sbt 2023-02-27 18:43:54 -08:00
Jenny Huang 475af86086 Merge branch 'generateChisel' of github.com:hqjenny/centrifuge into generateChisel 2022-10-03 17:21:34 -07:00
Jenny Huang 3159550d50 Add exception handling to compiler sim cmd 2022-10-03 17:21:28 -07:00
hqjenny 03f542b792 Add back WithClockGating 2020-04-01 01:31:20 +00:00
hqjenny 662ec8d47e Add FireSim compile/run scripts 2020-03-31 11:34:56 +00:00
Jenny Huang 04ad9ebeb5 Fix Chisel generation bug; Add VCS Simulation Commands 2020-03-30 02:43:16 -07:00
Jenny Huang 6b5429c9eb Fix hw generation bugs including not allowing understore in Config name; Fail to add Parameteres for HLS configs 2020-03-28 05:59:37 -07:00
Jenny Huang 968f89061b Add code to update verilog file to make it work in chipyard simulators 2020-03-28 05:39:55 -07:00
Jenny Huang e40c138316 Add generate config; Add argparse help and options 2020-03-19 08:15:26 -07:00
Jenny Huang c02423b576 Add generate build sbt script; renam run_chisel script 2020-03-18 04:20:45 -07:00
Jenny Huang 987f0b3e9a Add chisel generation code for tl 2020-03-17 03:23:46 -07:00
Jenny Huang d05c2998d8 Add chisel generation code for rocc 2020-03-16 04:20:26 -07:00
Jenny Huang 428e15d97d Merge branch 'python-dev' of github.com:hqjenny/centrifuge into python-dev 2020-02-11 13:48:16 -08:00
Jenny Huang fe03da65ca Change the hw prefix generation 2020-02-11 13:48:10 -08:00
Nathan Pemberton 5ecaac0881 Generate wrapper succesfully generates wrappers. I haven't verified that
the generated wrappers themselves work (but this was tested a while ago
so they should be close). This will require a slight change to
generate_hw to rename the verilog outputs to use accel.name to name
stuff.
2020-02-11 15:05:20 -05:00
Nathan Pemberton 249ed20178 Add in wrapper generation code (build_sw command). Previous versions
were tested, but this instance hasn't been yet.
2020-02-11 14:25:43 -05:00
Jenny Huang 0b9dce56de Fix python version, use pathlib and mv template folder 2020-02-08 02:04:44 -08:00
Jenny Huang 410eda4cc8 Add HLS scripts 2020-02-05 15:56:54 -08:00
Nathan Pemberton 6216088a93 Refactor around a pkg directory. Tested configuration system. 2020-02-04 20:04:59 -05:00
Nathan Pemberton 2859278016 First draft of configuration system. Not tested at all yet. 2020-02-04 17:00:33 -05:00
Jenny Huang b4d19ef241 Add python scripting for centrifuge 2019-11-04 13:48:16 -08:00