Previous debugging changes
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@ -17,12 +17,14 @@ def generate_build_sbt(accel_conf):
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accel_template = Template("""
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lazy val ${SOC_NAME} = (project in file("generators/${SOC_NAME}"))
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.dependsOn(boom, testchipip, hwacha, sifive_blocks, sifive_cache${ACCELS})
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.settings(chiselSettings)
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.settings(commonSettings)
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""")
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bm_template = Template("""
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lazy val ${ACCEL} = (project in file("${DIR}"))
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.dependsOn(rocketchip, testchipip, midasTargetUtils, icenet)
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.settings(chiselSettings)
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.settings(commonSettings)
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""")
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@ -205,7 +205,7 @@ def generate_opt_ap_signals(inputs, outputs):
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if 'ap_clk' in list(inputs.keys()):
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ret_str += " bb.io.ap_clk := clock\n"
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if 'ap_rst_n' in list(inputs.keys()):
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ret_str += " bb.io.ap_rst_n := !reset.toBool()\n"
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ret_str += " bb.io.ap_rst_n := !reset.asBool()\n"
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return ret_str
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@ -52,4 +52,4 @@ class HLSRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
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new freechips.rocketchip.system.BaseConfig)
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new chipyard.config.AbstractConfig)
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@ -14,13 +14,11 @@ class ApBusReq(dataWidth:Int, addrWidth:Int) extends Bundle{
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val address = UInt(OUTPUT, width = addrWidth)
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val dataout = UInt(OUTPUT, width = dataWidth)
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val size = UInt(OUTPUT, width = addrWidth)
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override def cloneType: this.type = new ApBusReq(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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//Response Packet Format
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class ApBusRsp(dataWidth:Int) extends Bundle{
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val datain = UInt(INPUT , width = dataWidth)
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override def cloneType: this.type = new ApBusRsp(dataWidth).asInstanceOf[this.type]
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}
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class ApBusIO(dataWidth:Int = 64, addrWidth:Int = 32) extends Bundle{
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@ -32,7 +30,6 @@ class ApBusIO(dataWidth:Int = 64, addrWidth:Int = 32) extends Bundle{
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val rsp = new ApBusRsp(dataWidth)
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val rsp_empty_n = Bool(INPUT )
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val rsp_read = Bool(OUTPUT)
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override def cloneType: this.type = new ApBusIO(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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class ApCtrlIO(dataWidth:Int = 64) extends Bundle{
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@ -43,5 +40,4 @@ class ApCtrlIO(dataWidth:Int = 64) extends Bundle{
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val idle = Bool(OUTPUT)
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val ready = Bool(OUTPUT)
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val rtn = UInt(OUTPUT, width = dataWidth)
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override def cloneType: this.type = new ApCtrlIO(dataWidth).asInstanceOf[this.type]
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}
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@ -40,7 +40,7 @@ val rs2_unbuffered = cmd.bits.rs2
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val idle :: working :: Nil = Enum(UInt(),2)
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val state = Reg(init=idle)
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when(reset.toBool){
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when(reset.asBool){
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bufferedCmd.inst.funct := 0.asUInt(7.W)
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bufferedCmd.inst.rs1 := 0.asUInt(5.W)
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bufferedCmd.inst.rs2 := 0.asUInt(5.W)
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