Add code to update verilog file to make it work in chipyard simulators

deploy/pkg/buildaccel/run_hls.py

@@ -1,5 +1,4 @@
-from __future__ import print_function
-import re
+
 
 import subprocess
 import random
@@ -7,6 +6,7 @@ import logging
 import json
 import os
 import shutil
+import pathlib
 from .. import util
 
 import errno    
@@ -17,6 +17,18 @@ logger = logging.getLogger(__name__)
 logger.setLevel(logging.NOTSET) 
 
 
+def modify_verilog(accel):
+    """ Update Verilog to make it compatible with our infrastructure
+        1. Add abs path to readmemh 
+        2. Replace undefined 'bx signals to 1'b0
+    """
+    verilog_dir = accel.verilog_dir
+    # list all verilog file
+    verilog_files = list(verilog_dir.glob('**/*.v'))
+    for verilog_file in verilog_files:
+        util.replace_str(verilog_file, '$readmemh("', "$readmemh(\"{}/".format(str(verilog_dir)))
+        util.replace_str(verilog_file, "'bx", "1'b0")
+
 def generate_hls_tcl(accel):
     """Generate TCL script to run Vivado HLS"""
 
@@ -77,4 +89,5 @@ def run_hls(accel_conf):
         generate_hls_tcl(accel)
         run_hls_cmd(accel)
         copy_verilog(accel)
-   
+        modify_verilog(accel)
+

deploy/pkg/util/util.py

@@ -2,8 +2,15 @@ import shutil
 import os
 import pathlib
 import errno
+import fileinput
+import sys
 from string import Template
 
+def replace_str(file_path, pattern, subst):
+    for line in fileinput.input(str(file_path), inplace=True):
+        if pattern in line:
+            line = line.replace(pattern, subst)
+        sys.stdout.write(line)
 
 def mkdir_p(path):
     try:

deploy/support/templates/Top_scala_template

@@ -0,0 +1,40 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.devices.tilelink._
+
+${HLS_SOC_IMPORT}
+// ------------------------------------
+// BOOM and/or Rocket Top Level Systems
+// ------------------------------------
+
+// DOC include start: Top
+class Top(implicit p: Parameters) extends System
+  with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
+  with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
+  with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
+  with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
+  with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
+  with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
+  with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
+  with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
+  with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
+${TL_TRAIT}
+{
+  override lazy val module = new TopModule(this)
+}
+
+class TopModule[+L <: Top](l: L) extends SystemModule(l)
+  with testchipip.CanHaveTraceIOModuleImp
+  with testchipip.CanHavePeripheryBlockDeviceModuleImp
+  with testchipip.CanHavePeripherySerialModuleImp
+  with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
+  with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
+  with icenet.CanHavePeripheryIceNICModuleImp
+  with chipyard.example.CanHavePeripheryGCDModuleImp
+  with freechips.rocketchip.util.DontTouch
+// DOC include end: Top