Add exception handling to compiler sim cmd
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parent
04ad9ebeb5
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3159550d50
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@ -15,7 +15,8 @@ def run_bm_sw(accel_conf, simulator, bm_sw_path):
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cmd_arr = cmd.split()
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subprocess.check_call(cmd_arr, cwd=sims_dir)
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def compile_sim_cmd(accel_conf, simulator, cmd=""):
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def compile_sim_cmd(accel_conf, simulator, cmd="", check_call=True):
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clean_str = "";
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sims_dir = accel_conf.sims_dir / simulator
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@ -24,13 +25,17 @@ def compile_sim_cmd(accel_conf, simulator, cmd=""):
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logger.info("\t\tCommand: {}".format(cmd))
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cmd_arr = cmd.split()
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subprocess.check_call(cmd_arr, cwd=sims_dir)
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try:
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subprocess.check_call(cmd_arr, cwd=sims_dir)
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except Exception:
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if check_call:
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raise()
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def run_sim(accel_conf, simulator, subtask, bm_sw_path=None):
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if subtask is None:
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compile_sim_cmd(accel_conf, simulator, 'clean')
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compile_sim_cmd(accel_conf, simulator, 'debug')
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compile_sim_cmd(accel_conf, simulator, 'debug', False)
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append_verilog_to_top_v(accel_conf, simulator)
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compile_sim_cmd(accel_conf, simulator, 'debug')
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else:
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