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Add dprv connection for new Chipyard HellaCacheIO

This commit is contained in:
Jenny Huang 2023-06-05 22:47:02 -07:00
parent 3887cac15c
commit 7c0a7f7177
2 changed files with 6 additions and 1 deletions
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3
deploy/support/templates/chisel_rocc_accel_scala_template
View File

@ -60,6 +60,9 @@ io.resp.bits.data := result
io.busy := busy
cmd.ready := rdy
// Set the HellaCache req privilege to rocc command privilege
io.mem.req.bits.dprv := io.cmd.bits.status.dprv
//===== Begin Accelerator =====
val accel = Module(new HLS${FUNC}Blackbox())

4
examples/vadd/vadd.c
View File

@ -13,7 +13,8 @@ void print_vec(int* vec, int length){
}
int main () {
int length_a[LENGTH + 1], b_c[LENGTH + LENGTH];
int length_a[LENGTH + 1] __attribute__((aligned(64)));
int b_c[LENGTH + LENGTH] __attribute__((aligned(64)));
//int a[LENGTH], b[LENGTH], c[LENGTH];
int length = LENGTH;
length_a[0] = length;
@ -23,6 +24,7 @@ int main () {
b_c[i] = i + 5;
}
printf("length_a ptr: %X", length_a);
uint64_t begin, end, dur;
begin = read_cycle();
vadd(length_a, b_c);