ca320f54da
fix this to build with the recent StructType changes.
...
llvm-svn: 129139
2011-04-08 17:56:47 +00:00
18b81c52bb
Refactor MCJIT 32-bit section loading.
...
Teach 32-bit section loading to use the Memory Manager interface, just like
the 64-bit loading does. Tidy up a few other things here and there.
llvm-svn: 129138
2011-04-08 17:31:24 +00:00
74c74ba81c
MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.
...
Add tests for that.
llvm-svn: 129137
2011-04-08 17:29:58 +00:00
466d0c1f93
llvm.global_[cd]tor is defined to be either external, or appending with an array
...
of { i32, void ()* }. Teach the verifier to verify that, deleting copies of
checks strewn about.
llvm-svn: 129128
2011-04-08 07:30:21 +00:00
33984c6973
Only emit the AvailableFeatures variable if it's used.
...
llvm-svn: 129124
2011-04-08 04:08:57 +00:00
a21d470870
Also add the late notes for Mips in the current release note
...
llvm-svn: 129122
2011-04-08 03:06:22 +00:00
7e51b4640f
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
...
Add more test cases to exercise the logical branches related to the above change.
llvm-svn: 129117
2011-04-08 00:29:09 +00:00
9a1a34b105
Update tests
...
llvm-svn: 129116
2011-04-07 23:51:25 +00:00
b80875edee
Micro optimization and improved similarity with gas' output:
...
When two section names share a suffix, reuse the entry in shstrtab.
llvm-svn: 129115
2011-04-07 23:21:52 +00:00
bc3d8b212f
Do not let debug info interfer with branch folding.
...
llvm-svn: 129114
2011-04-07 23:11:25 +00:00
165a07adf9
Add a VEXT test.
...
llvm-svn: 129111
2011-04-07 22:04:01 +00:00
bc3f79044a
Replace the old algorithm that emitted the "print the alias for an instruction"
...
with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.
There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.
llvm-svn: 129110
2011-04-07 21:20:06 +00:00
ece7c9c282
If present, use gold's support for getting a file view. This prevents having
...
to map the file both in the linker and in the plugin.
llvm-svn: 129109
2011-04-07 21:11:00 +00:00
9a3f2772f0
Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183.
...
llvm-svn: 129107
2011-04-07 20:31:12 +00:00
88bc341061
Add support for .skip.
...
Patch by Roman Divacky.
Fixes PR9361.
llvm-svn: 129106
2011-04-07 20:26:23 +00:00
052163e6d3
Fix indentation.
...
llvm-svn: 129105
2011-04-07 20:25:10 +00:00
94ee37e487
Update ATUsed every time after expandRegLargeImmPair is called.
...
llvm-svn: 129104
2011-04-07 20:23:26 +00:00
27f3330132
Fixed encoding for VEXTqf
...
llvm-svn: 129101
2011-04-07 19:56:12 +00:00
2ad0b37318
Added a check in the preRA scheduler for potential interference on a
...
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.
Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing
llvm-svn: 129100
2011-04-07 19:54:57 +00:00
d6f1c58914
Fix handling of functions with internal linkage.
...
llvm-svn: 129099
2011-04-07 19:51:44 +00:00
04efb8f6ce
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
...
Add some test cases.
llvm-svn: 129098
2011-04-07 19:28:58 +00:00
07606661f9
Add sanity checking for invalid register encodings for saturating instructions.
...
llvm-svn: 129096
2011-04-07 19:02:08 +00:00
64beb47783
Recompute hasPHIKill flags when shrinking live intervals.
...
PHI values may be deleted, causing the flags to be wrong. This fixes PR9616.
llvm-svn: 129092
2011-04-07 18:43:14 +00:00
194a2267ad
Add some more comments about checkings of invalid register numbers.
...
And two test cases.
llvm-svn: 129090
2011-04-07 18:33:19 +00:00
e4e4e37580
Expose more passes to the C API.
...
llvm-svn: 129087
2011-04-07 18:20:46 +00:00
994c16833c
Avoid moving iterators when the previous block was just visited.
...
llvm-svn: 129081
2011-04-07 17:27:50 +00:00
1c0db0fd21
Prefer multiplications to divisions.
...
llvm-svn: 129080
2011-04-07 17:27:48 +00:00
6d2bbc1c20
Extract SpillPlacement::addLinks for handling the special transparent blocks.
...
llvm-svn: 129079
2011-04-07 17:27:46 +00:00
197c35298a
While hoisting common code from if/else, hoist debug info intrinsics if they match.
...
llvm-svn: 129078
2011-04-07 17:27:36 +00:00
266792a55a
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
...
llvm-svn: 129074
2011-04-07 15:24:20 +00:00
65bef04ea7
Fix a bit of nonsense.
...
llvm-svn: 129073
2011-04-07 12:41:09 +00:00
5ddaab1789
add faust too
...
llvm-svn: 129053
2011-04-07 03:09:21 +00:00
caefe9346d
add a few late stragglers.
...
llvm-svn: 129052
2011-04-07 03:08:22 +00:00
6c6be946fc
Fixed a bug where missing EDInstInfo would cause
...
tokenization to crash and burn.
llvm-svn: 129051
2011-04-07 01:56:01 +00:00
313ec7953a
Sanity check MSRi for invalid mask values and reject it as invalid.
...
rdar://problem/9246844
llvm-svn: 129050
2011-04-07 01:37:34 +00:00
c5f22a7815
PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoad
...
is equivalent to any other relevant value; it isn't true in general.
If it is equivalent, the LoopPromoter will tell the AST the equivalence.
Also, delete the PreheaderLoad if it is unused.
Chris, since you were the last one to make major changes here, can you check
that this is sane?
llvm-svn: 129049
2011-04-07 01:35:06 +00:00
c0e86fb965
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
...
for USAD8 and USADA8.
rdar://problem/9247060
llvm-svn: 129047
2011-04-07 01:05:52 +00:00
a7c7b54dde
Change -arm-divmod-libcall to a target neutral option.
...
llvm-svn: 129045
2011-04-07 00:58:44 +00:00
b7c9c407f9
Remove dead code. rdar://9221736.
...
llvm-svn: 129044
2011-04-07 00:56:37 +00:00
d4cced54b3
Should also check SMLAD for invalid register values.
...
rdar://problem/9246650
llvm-svn: 129042
2011-04-07 00:50:25 +00:00
e48ddf863b
Simplify. isIdenticalToWhenDefined() checks opcode.
...
llvm-svn: 129041
2011-04-07 00:30:15 +00:00
561f1755cc
Set unnamed_addr on strings created through the IRBuilder.
...
llvm-svn: 129040
2011-04-07 00:14:29 +00:00
9363fdc9b7
Add support for ArrayRef in IRBuilder's CreateCall.
...
llvm-svn: 129039
2011-04-07 00:03:25 +00:00
bdff1c997a
Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
...
llvm-svn: 129038
2011-04-06 23:35:59 +00:00
f9bd6bad8a
Cleanups from Jim: remove redundant constraints and a dead FIXME.
...
llvm-svn: 129036
2011-04-06 22:45:55 +00:00
d715ec82b4
While folding branch to a common destination into a predecessor, copy dbg values also.
...
llvm-svn: 129035
2011-04-06 22:37:20 +00:00
6ade7e0bac
Tidy up.
...
llvm-svn: 129034
2011-04-06 22:35:47 +00:00
bd9a4f8d07
A8.6.393
...
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
llvm-svn: 129033
2011-04-06 22:14:48 +00:00
9c14679260
tidy up.
...
llvm-svn: 129032
2011-04-06 22:13:52 +00:00
8ce2f43694
Also account for the spill code that would be inserted in live-through blocks with interference.
...
llvm-svn: 129030
2011-04-06 21:32:41 +00:00
81439a83f4
Abort the constraint calculation early when all positive bias is lost.
...
Without any positive bias, there is nothing for the spill placer to to. It will
spill everywhere.
llvm-svn: 129029
2011-04-06 21:32:38 +00:00
469d171ae2
Fix typo in doxy-comment.
...
llvm-svn: 129028
2011-04-06 20:54:07 +00:00
2ac486e387
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
...
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
llvm-svn: 129027
2011-04-06 20:49:02 +00:00
0cbfcb2b6d
Fix comment to use llvm 2.x syntax.
...
llvm-svn: 129025
2011-04-06 20:38:44 +00:00
e30f330393
Replace const std::vector& with ArrayRef in the type creation APIs.
...
llvm-svn: 129024
2011-04-06 20:28:34 +00:00
6895b87dfe
Keep track of the number of positively biased nodes when adding constraints.
...
If there are no positive nodes, the algorithm can be aborted early.
llvm-svn: 129021
2011-04-06 19:14:00 +00:00
36b5d8a698
Break the spill placement algorithm into three parts: prepare, addConstraints, and finish.
...
This will allow us to abort the algorithm early if it is determined to be futile.
llvm-svn: 129020
2011-04-06 19:13:57 +00:00
620f6967e0
Fix a typo.
...
llvm-svn: 129019
2011-04-06 19:12:21 +00:00
8bca174f48
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
...
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
llvm-svn: 129015
2011-04-06 18:27:46 +00:00
b4dd95b4f9
Add another case we are not optimizing.
...
llvm-svn: 129012
2011-04-06 17:35:32 +00:00
7a3b244d45
The original issue has been fixed by not doing unnecessary sign extensions.
...
Change the test to force a sign extension and expose the problem again.
llvm-svn: 129011
2011-04-06 17:19:35 +00:00
8aa6c326ac
face+palm
...
Keep track of llvm.dbg.value intrinsics with non null values.
llvm-svn: 129010
2011-04-06 17:08:15 +00:00
337a1b29e5
Do a topological sort of the types before writing them out.
...
This takes the linking of libxul on linux from 6m54.931s to 5m39.840s.
llvm-svn: 129009
2011-04-06 16:49:37 +00:00
300504c135
EngineBuilder setter method for UseMCJIT was missing return value.
...
llvm-svn: 129008
2011-04-06 16:35:19 +00:00
958d299fca
add rubinius
...
llvm-svn: 129006
2011-04-06 16:14:25 +00:00
87e3367d32
Fix a few instances of "warning: extra ';' outside of a function [-pedantic]".
...
llvm-svn: 129002
2011-04-06 12:29:56 +00:00
cc771acd77
This testcase passed even without the fix. Added the target info to make the
...
test fail (without the fix). Thanks Dan.
llvm-svn: 128999
2011-04-06 11:18:29 +00:00
ce5d9aedb9
Fix some typos. Minor tweaks to how some things were expressed.
...
llvm-svn: 128997
2011-04-06 08:07:40 +00:00
1a7cc44157
Trivial typo fixes.
...
llvm-svn: 128996
2011-04-06 07:55:30 +00:00
d4b3d29c50
Add an empty key for DebugLoc so that you can store an empty DebugLoc in a
...
DenseMap.
llvm-svn: 128994
2011-04-06 06:49:59 +00:00
17c170a8e0
Finish up the first draft of the release notes.
...
improvements are welcome, please commit any changes directly to SVN.
llvm-svn: 128992
2011-04-06 06:29:50 +00:00
23e16b59d2
continue writing.
...
llvm-svn: 128990
2011-04-06 05:50:04 +00:00
ddc72895d0
Support using DebugLoc's in a DenseMap.
...
llvm-svn: 128988
2011-04-06 05:36:52 +00:00
f3b2dcc74d
Oops. Scary.
...
llvm-svn: 128986
2011-04-06 04:07:14 +00:00
bf91c4e85e
Analyze blocks with uses separately from live-through blocks without uses.
...
About 90% of the relevant blocks are live-through without uses, and the only
information required about them is their number. This saves memory and enables
later optimizations that need to look at only the use-blocks.
llvm-svn: 128985
2011-04-06 03:57:00 +00:00
0ec0e98a6a
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
...
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
llvm-svn: 128977
2011-04-06 01:18:32 +00:00
ae6a89a890
add the external users that emailed me.
...
llvm-svn: 128974
2011-04-06 01:13:49 +00:00
23de2437bd
RuntimeDyld should use the memory manager API.
...
Start teaching the runtime Dyld interface to use the memory manager API
for allocating space. Rather than mapping directly into the MachO object,
we extract the payload for each object and copy it into a dedicated buffer
allocated via the memory manager. For now, just do Segment64, so this works
on x86_64, but not yet on ARM.
llvm-svn: 128973
2011-04-06 01:11:05 +00:00
14a3333cb3
some libc++ notes.
...
llvm-svn: 128970
2011-04-06 00:59:18 +00:00
9d5b3712de
some edits.
...
llvm-svn: 128969
2011-04-06 00:56:12 +00:00
c3a2c9817c
distribute content out to the appropriate sections
...
llvm-svn: 128968
2011-04-06 00:45:11 +00:00
867846b1f0
Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
...
llvm-svn: 128965
2011-04-05 23:55:28 +00:00
086f7080d6
Make the virtual destructor out-of-line so we have a key function.
...
llvm-svn: 128964
2011-04-05 23:54:31 +00:00
858afbb6ac
Sign error
...
llvm-svn: 128963
2011-04-05 23:43:16 +00:00
5c482cd38f
Don't crash when a value is defined after the last split point.
...
llvm-svn: 128962
2011-04-05 23:43:14 +00:00
30b5473d82
Permit blocks to branch directly to a landing pad.
...
Treat the landing pad as a normal successor when that happens.
llvm-svn: 128961
2011-04-05 23:43:11 +00:00
f642c1b600
Remove extraneous 'return'.
...
llvm-svn: 128959
2011-04-05 23:39:08 +00:00
f6e327c6a3
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
...
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
llvm-svn: 128958
2011-04-05 23:28:00 +00:00
ce6b047a10
finished my pass through all the 2.9 commits, now to make this intelligible
...
llvm-svn: 128955
2011-04-05 23:22:33 +00:00
a76507fdc3
mention llvm::ArrayRef, which should be use much more pervasively than
...
it already is.
llvm-svn: 128954
2011-04-05 23:18:20 +00:00
d135c696c0
Clean up some code for clarity.
...
llvm-svn: 128953
2011-04-05 23:03:25 +00:00
f920fbf94b
Provide an empty virtual destructor to go with the virtual methods in
...
this class. Clang was warning on this with -Wnon-virtual-dtor.
llvm-svn: 128952
2011-04-05 23:03:24 +00:00
61e7a935bd
Revert r128946 while I figure out why it broke the buildbots.
...
llvm-svn: 128951
2011-04-05 23:03:06 +00:00
c3656d29f6
A7.3 register encoding
...
Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
llvm-svn: 128949
2011-04-05 22:57:07 +00:00
9f738849ab
Add support to encode function's template parameters.
...
llvm-svn: 128947
2011-04-05 22:52:06 +00:00
3501655ad9
Give RSBS and RSCS the pseudo treatment.
...
llvm-svn: 128946
2011-04-05 22:42:54 +00:00
9da60e016b
ARM disassembler was erroneously accepting an invalid RSC instruction.
...
Added checks for regs which should not be 15.
rdar://problem/9237734
llvm-svn: 128945
2011-04-05 22:18:07 +00:00
57ee5a5db7
remove postdom frontiers, because it is dead. Forward dom frontiers are
...
still used by RegionInfo :(
llvm-svn: 128943
2011-04-05 21:57:17 +00:00
530d739097
docs/ReleaseNotes.html: Please use proper *Heading* elements instead of classified div.
...
It would be better to browse without stylesheet. (eg. on ViewVC)
llvm-svn: 128942
2011-04-05 21:55:14 +00:00
25883487a1
ARM disassembler was erroneously accepting an invalid LSL instruction.
...
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
llvm-svn: 128941
2011-04-05 21:49:44 +00:00
77aa266de8
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
...
llvm-svn: 128940
2011-04-05 21:48:57 +00:00
706754c1f2
remove graphprinter support for domfrontier.
...
llvm-svn: 128938
2011-04-05 21:43:56 +00:00
1ec41e2bd9
These tests no longer require linear scan because reserved register coalescing is now universal.
...
llvm-svn: 128936
2011-04-05 21:40:41 +00:00
6aa0fbf4c0
Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.
...
llvm-svn: 128935
2011-04-05 21:40:37 +00:00
269ef9f6f0
only 7 more weeks to go.
...
llvm-svn: 128933
2011-04-05 21:37:08 +00:00
d4e20eacf0
Refactor.
...
llvm-svn: 128929
2011-04-05 21:08:24 +00:00
04123d40cd
Document llvm/ADT/IntEqClasses.h in ProgrammersManual.html
...
llvm-svn: 128927
2011-04-05 20:56:08 +00:00
6c20b88173
Add an assertion instead of crashing when the scavenger goes past the end
...
of a basic block.
llvm-svn: 128925
2011-04-05 20:44:15 +00:00
ee54fa29d5
Fix typos. Adjust some whitespace for style. No functionality change.
...
llvm-svn: 128924
2011-04-05 20:39:27 +00:00
e9c644d4a0
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
...
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/9236873
llvm-svn: 128922
2011-04-05 20:32:23 +00:00
92d313a021
Add support for detection of Intel SandyBridge.
...
llvm-svn: 128920
2011-04-05 20:25:36 +00:00
e20fec7732
Fix one more batch of X86 tests to be register allocation dependent.
...
llvm-svn: 128919
2011-04-05 20:20:30 +00:00
18fd84c79a
When dead code elimination removes all but one use, try to fold the single def into the remaining use.
...
Rematerialization can leave single-use loads behind that we might as well fold whenever possible.
llvm-svn: 128918
2011-04-05 20:20:26 +00:00
651d06e036
Do not emit empty name.
...
llvm-svn: 128914
2011-04-05 20:14:13 +00:00
151582492d
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
...
llvm-svn: 128913
2011-04-05 19:42:11 +00:00
40d388c25e
Fix a typo.
...
llvm-svn: 128912
2011-04-05 19:13:11 +00:00
12004013ef
Added *hidden* flags -print-options and -print-all-options so
...
developers can see if their driver changed any cl::Option's. The
current implementation isn't perfect but handles most kinds of
options. This is nice to have when decomposing the stages of
compilation and moving between different drivers. It's also a good
sanity check when comparing results produced by different command line
invocations that are expected to produce the comparable results.
Note: This is not an attempt to prolong the life of cl::Option. On the
contrary, it's a placeholder for a feature that must exist when
cl::Option is replaced by a more appropriate framework. A new
framework needs: a central option registry, dynamic name lookup,
non-global containers of option values (e.g. per-module,
per-function), *and* the ability to print options values and their defaults at
any point during compilation.
llvm-svn: 128910
2011-04-05 18:54:36 +00:00
56c15c64b0
LDRD now prints out two dst registers.
...
llvm-svn: 128909
2011-04-05 18:53:14 +00:00
293875ef55
Fix test-llvm failures.
...
llvm-svn: 128906
2011-04-05 18:41:40 +00:00
b826ae8310
whitespace
...
llvm-svn: 128905
2011-04-05 18:41:31 +00:00
e59f8ca49e
An MCDisassembler has the option to not implement
...
getEDInfo(), in which case this code would dereference
NULL. EDInst can already handle NULL info, so avoid
the dereference and pass NULL through.
Reviewed by Sean Callanan
llvm-svn: 128904
2011-04-05 18:40:45 +00:00
d9dce561b6
Make second source operand of LDRD pre/post explicit.
...
Finish what r128736 started.
llvm-svn: 128903
2011-04-05 18:40:13 +00:00
9ee0b01617
more notes to self.
...
llvm-svn: 128902
2011-04-05 18:38:45 +00:00
33d3a9fadc
Constants with multiple encodings (ARM):
...
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
llvm-svn: 128897
2011-04-05 18:02:46 +00:00
268d63f307
Check for invalid register encodings for UMAAL and friends where:
...
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;
rdar://problem/9230202
llvm-svn: 128895
2011-04-05 17:43:10 +00:00
f7678b83d2
Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
...
llvm-svn: 128892
2011-04-05 17:24:25 +00:00
345094777f
ARM doesn't support byval yet. XFAIL this test until it does.
...
llvm-svn: 128891
2011-04-05 17:16:21 +00:00
d8a6dd6c99
Rename LLVMConfig.cmake to LLVM-Config.cmake. The *Config.cmake naming
...
scheme is used by the functionality related to find_package.
llvm-svn: 128889
2011-04-05 17:02:48 +00:00
76ad3debab
Ensure all defs referring to a virtual register are marked dead by addRegisterDead().
...
There can be multiple defs for a single virtual register when they are defining
sub-registers.
The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.
llvm-svn: 128888
2011-04-05 16:53:50 +00:00
7dd4d6e2e8
Print visibility info for external variables.
...
llvm-svn: 128887
2011-04-05 15:51:32 +00:00
fe6e07fd8a
Use std::unique instead of a SmallPtrSet to ensure unique instructions in UseSlots.
...
This allows us to always keep the smaller slot for an instruction which is what
we want when a register has early clobber defines.
Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed.
llvm-svn: 128886
2011-04-05 15:18:18 +00:00
a069c6ce05
InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away address
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space info. We crash with an assert in this case. This change checks that the
address space of the bitcasted pointer is the same as the gep ptr.
llvm-svn: 128884
2011-04-05 14:29:52 +00:00
8d89b8e684
docs/ReleaseNotes.html: Add a few notes to MCCOFF and x64. FIXME: fixme!
...
llvm-svn: 128882
2011-04-05 08:24:22 +00:00
f8e44c35eb
docs/GettingStarted.html: FIXME: dg, lit, and source tree layout.
...
llvm-svn: 128881
2011-04-05 08:24:15 +00:00
fd97b88b2f
add a bunch of notes to myself, this is not intended to be gramatic or
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make sense to anyone else.
llvm-svn: 128879
2011-04-05 07:19:28 +00:00
d93b0e3ced
Stop precomputing last split points, query the SplitAnalysis cache on demand.
...
llvm-svn: 128875
2011-04-05 04:20:29 +00:00
50b2db8a02
Cache the fairly expensive last split point computation and provide a fast
...
inlined path for the common case.
Most basic blocks don't contain a call that may throw, so the last split point
os simply the first terminator.
llvm-svn: 128874
2011-04-05 04:20:27 +00:00
dd4dcd549b
Revamp the SjLj "dispatch setup" intrinsic.
...
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>
llvm-svn: 128873
2011-04-05 01:37:43 +00:00
f392a69ff7
Fix up testcase for previous commit.
...
llvm-svn: 128870
2011-04-05 00:56:01 +00:00
b968f4defe
Just use BL all the time. It's safer that way.
...
Fixes rdar://9184526
llvm-svn: 128869
2011-04-05 00:39:26 +00:00
ad68c93a2d
Revert 123704; it broke threaded LLVM.
...
llvm-svn: 128868
2011-04-05 00:37:28 +00:00
bd09d45489
Fix register-dependent X86 tests.
...
llvm-svn: 128867
2011-04-05 00:32:44 +00:00
9b3ccba636
Fix SRS/SRSW encoding bits.
...
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859 .
llvm-svn: 128864
2011-04-05 00:16:18 +00:00
782a60c117
A8.6.105 MUL
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Inst{15-12} should be specified as 0b0000.
rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL
llvm-svn: 128862
2011-04-04 23:57:05 +00:00
db62424c3d
Add info on where to get 2.9 final svn sources.
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llvm-svn: 128860
2011-04-04 23:42:51 +00:00
a6129b4a7f
RFE encoding should also specify the "should be" encoding bits.
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rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE
Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.
llvm-svn: 128859
2011-04-04 23:39:08 +00:00
b070fd655d
Add missing file from r128851.
...
llvm-svn: 128856
2011-04-04 23:20:40 +00:00
2dcef0505f
Layer the memory manager between the JIT and the runtime Dyld.
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The JITMemory manager references LLVM IR constructs directly, while the
runtime Dyld works at a lower level and can handle objects which may not
originate from LLVM IR. Introduce a new layer for the memory manager to
handle the interface between them. For the MCJIT, this layer will be almost
entirely simply a call-through w/ translation between the IR objects and
symbol names.
llvm-svn: 128851
2011-04-04 23:04:39 +00:00
418f186a4b
Make OpcodeMask an unsigned long long literal to deal with overflow.
...
llvm-svn: 128847
2011-04-04 21:38:17 +00:00
2e85396509
Allow coalescing with reserved physregs in certain cases:
...
When a virtual register has a single value that is defined as a copy of a
reserved register, permit that copy to be joined. These virtual register are
usually copies of the stack pointer:
%vreg75<def> = COPY %ESP; GR32:%vreg75
MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill>
MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0
MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0
CALLpcrel32 ...
Coalescing these virtual registers early decreases register pressure.
Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after
register allocation was completed.
The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail
because it depends on linear scan spilling a particular register.
I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of
instructions emitted, and its revision history shows the 'correct' count being
edited many times.
llvm-svn: 128845
2011-04-04 21:00:03 +00:00
8de5ca72e3
Extract physreg joining policy to a separate method.
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llvm-svn: 128844
2011-04-04 20:59:59 +00:00
8372006296
Fix incorrect alignment for NEON VST2b32_UPD.
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rdar://problem/9225433
llvm-svn: 128841
2011-04-04 20:35:31 +00:00
0abc463f5b
Update BreakpointPrinter to emit original function names only.
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llvm-svn: 128839
2011-04-04 19:51:17 +00:00
13ce236c4c
Insert code in the right location when lowering PowerPC atomics.
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This causes defs to dominate uses, no instructions after terminators, and other
goodness.
llvm-svn: 128836
2011-04-04 17:57:29 +00:00
8296e30627
Disable the PowerPC/Atomics-64 test.
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The code inserted by PPCTargetLowering::EmitInstrWithCustomInserter for ppc64 is
wrong, and I don't know how to fix it. It seems to be using the correct register
classes for pointers, but it inserts all 32-bit instructions.
llvm-svn: 128835
2011-04-04 17:57:26 +00:00
66c1c59bdb
Remove unused function.
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llvm-svn: 128834
2011-04-04 17:36:11 +00:00
bda3632bcd
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
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also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
llvm-svn: 128832
2011-04-04 17:18:19 +00:00
2c6cefc9c3
silence an unused function warning.
...
llvm-svn: 128831
2011-04-04 17:17:57 +00:00
5ec2ead9b0
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
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llvm-svn: 128830
2011-04-04 17:11:07 +00:00
86e1a65ce5
PowerPC atomic pseudos clobber CR0, they don't read it.
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llvm-svn: 128829
2011-04-04 17:07:09 +00:00
7067bff976
Use X0 instead of R0 for the zero register on ppc64.
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The 32-bit R0 cannot be used where a 64-bit register is expected.
llvm-svn: 128828
2011-04-04 17:07:06 +00:00
218661346a
Fix PowerPC tests to be register allocator independent.
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llvm-svn: 128827
2011-04-04 17:07:03 +00:00
fc4789da4a
Add support for the VIA PadLock instructions.
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llvm-svn: 128826
2011-04-04 16:58:13 +00:00
c94780c539
Use array_lengthof
...
llvm-svn: 128823
2011-04-04 16:25:38 +00:00
cc53d9919f
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
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Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.
llvm-svn: 128822
2011-04-04 15:58:30 +00:00
8933907b51
Stop caching basic block index ranges now that SlotIndexes can keep up.
...
llvm-svn: 128821
2011-04-04 15:32:15 +00:00
956ae3da41
Delete leftover data members.
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llvm-svn: 128820
2011-04-04 15:32:11 +00:00
fb3bce155e
Change loops to derive the number of tables automatically
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llvm-svn: 128818
2011-04-04 14:42:22 +00:00
1cd7898dc1
Dragonegg release notes.
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llvm-svn: 128812
2011-04-04 11:09:08 +00:00
11522097be
Remove some support for ReturnInsts with multiple operands, and for
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returning a scalar value in a function whose return type is a single-
element structure or array.
llvm-svn: 128810
2011-04-04 07:44:02 +00:00
8b304ff9ac
Region: Allow user control the printing style of the print function.
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Contributed by: etherzhhb@gmail.com
llvm-svn: 128808
2011-04-04 07:19:18 +00:00
2642d34551
IntrusiveRefCntPtr: in RefCountedBase and RefCountedBaseVPTR, make
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ref_cnt mutable and Retain/Release const to enable reference counted
pointers to const objects
llvm-svn: 128804
2011-04-04 00:57:03 +00:00
b85c0caf7d
Attempt to fix breakage from r128782 reported by Francois Pichet on
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llvm-commits. (Not sure why it only breaks on Windows; maybe it has
something to do with the iterator representation...)
llvm-svn: 128802
2011-04-04 00:37:38 +00:00
19ea5ae81a
Start migrating mach-o dumping facilities to the object file out of a
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separate executable.
llvm-svn: 128801
2011-04-03 23:51:47 +00:00
c56d2e8fd0
Move Object.cpp out of VMCore and into Object.
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llvm-svn: 128800
2011-04-03 23:07:51 +00:00
ee066fc4f3
Assorted bugfixes in object file handling:
...
- Adds support for sniffing PE/COFF files on win32 (.exe and .dll)
which are COFF files that have an MS-DOS compatibility stub on
the front of them.
- Fixes a bug in the COFFObjectFile's support for the Microsoft COFF
extension for long symbol names, wherein it was attempting to parse
the leading '/' in an extended symbol name reference as part of the
integer offset.
- Fixes bugs in COFFObjectFile and ELFObjectFile wherein section
and symbol iterators were being returned with uninitialized bytes;
the type DataRefImpl is a union between 2 32-bit words (d.a and d.b)
and a single intptr_t word (p). Only p was being initialized, so in
32-bit builds the result would be iterators with random upper 32-bit
words in their DataRefImpls. This caused random failures when
seeking around in object files.
Patch by Graydon Hoare!
llvm-svn: 128799
2011-04-03 22:53:19 +00:00
9f08a3bbf4
Add a set of C bindings for the Object interface.
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Patch by Patrick Walton!
llvm-svn: 128798
2011-04-03 22:34:07 +00:00
614a2fdbd1
Remove the LLVMContext& arguments from *Folder constructors, as they don't seem to be used anywhere.
...
llvm-svn: 128793
2011-04-03 19:46:28 +00:00
8b29cf50ed
Fix typos on LLVM.cmake. Export LLVM_ON_UNIX & LLVM_ON_WIN32.
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Patch by arrowdodger!
llvm-svn: 128789
2011-04-03 16:12:38 +00:00
17bf4922c9
PR9446: RecursivelyDeleteTriviallyDeadInstructions can delete the instruction
...
after the given instruction; make sure to handle that case correctly.
(It's difficult to trigger; the included testcase involves a dead
block, but I don't think that's a requirement.)
While I'm here, get rid of the unnecessary warning about
SimplifyInstructionsInBlock, since it should work correctly as far as I know.
llvm-svn: 128782
2011-04-02 22:45:17 +00:00
8baa2c7ad9
Don't assume something which might be a constant expression is an instruction.
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Based on PR9429, but no testcase because I can't figure out how to trigger it
anymore given other changes to the relevant code.
llvm-svn: 128781
2011-04-02 22:11:56 +00:00
50a281a871
While SimplifyDemandedBits constant folds this, we can't rely on it here.
...
It's possible to craft an input that hits the recursion limits in a way
that SimplifyDemandedBits doesn't simplify the icmp but ComputeMaskedBits
can infer which bits are zero.
No test case as it depends on too many other things. Fixes PR9609.
llvm-svn: 128777
2011-04-02 18:50:58 +00:00
f2ab92833a
Handle changing of LLVM_ENABLE_FFI.
...
If someone first configure build with LLVM_ENABLE_FFI=1 and then turn it
off, the build will fail in lib/ExecutionEngine/Interpreter because
Interpreter will try still to #include <ffi/ffi.h>, but there are no
include_directories(${FFI_INCLUDE_DIR}) now.
This patch unset()'s HAVE_FFI_H and HAVE_FFI_FFI_H from cache file if
LLVM_ENABLE_FFI=0. This forces CMake to update config.h.
Patch by arrowdodger!
llvm-svn: 128769
2011-04-02 13:21:12 +00:00
e34b271718
ptx: support setp's 4-operand format
...
llvm-svn: 128767
2011-04-02 08:51:39 +00:00
ca26e0acbb
Use InterferenceCache in RegAllocGreedy.
...
llvm-svn: 128765
2011-04-02 06:03:38 +00:00
91cbcaf957
Add an InterferenceCache class for caching per-block interference ranges.
...
When the greedy register allocator is splitting multiple global live ranges, it
tends to look at the same interference data many times. The InterferenceCache
class caches queries for unaltered LiveIntervalUnions.
llvm-svn: 128764
2011-04-02 06:03:35 +00:00
36171288ce
Use basic block numbers as indexes when mapping slot index ranges.
...
This is more compact and faster than using DenseMap.
llvm-svn: 128763
2011-04-02 06:03:31 +00:00
6fe5c29430
Do some peephole optimizations to remove pointless VMOVs from Neon to integer
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registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.
llvm-svn: 128759
2011-04-02 02:40:43 +00:00
8c7bbc09e2
Add a RemoveFromWorklist method to DCI. This is needed to do some complicated
...
transformations in target-specific DAG combines without causing DAGCombiner to
delete the same node twice. If you know of a better way to avoid this (see my
next patch for an example), please let me know.
llvm-svn: 128758
2011-04-02 02:40:26 +00:00
8904cc49db
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
...
instead of the second operand in addrmode_imm12.
rdar://problem/9225289
llvm-svn: 128757
2011-04-02 02:24:54 +00:00
4111db6575
Undo changes mistakenly made in revision 128750.
...
llvm-svn: 128751
2011-04-02 00:26:12 +00:00
977f555a76
Insert space before ';' to prevent warnings.
...
llvm-svn: 128750
2011-04-02 00:15:58 +00:00
387b36eaae
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
...
rdar://problem/9224276
llvm-svn: 128749
2011-04-01 23:30:25 +00:00
6615fa1de0
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
...
rdar://problem/9224120
llvm-svn: 128748
2011-04-01 23:15:50 +00:00
1e1010f56f
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
...
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
llvm-svn: 128746
2011-04-01 22:32:51 +00:00
8b94c295c3
Fix comment.
...
llvm-svn: 128745
2011-04-01 22:29:18 +00:00
5cad45307e
Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments:
...
- Localize the check if an icmp has one use to a place where we know we're
introducing something that's likely more expensive than a sext from i1.
- Add an assert to make sure a case that would lead to a miscompilation is
folded away earlier.
- Fix a typo.
llvm-svn: 128744
2011-04-01 22:22:11 +00:00
88530e6568
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
...
llvm-svn: 128743
2011-04-01 22:09:28 +00:00
3d9df607ba
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
...
llvm-svn: 128742
2011-04-01 21:56:02 +00:00
56d9ef53a2
Simplifies logic for printing target flags.
...
llvm-svn: 128741
2011-04-01 21:41:06 +00:00
Chris Lattner