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Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that 

all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094

llvm-svn: 128746
This commit is contained in:
Johnny Chen 2011-04-01 22:32:51 +00:00
parent 8b94c295c3
commit 1e1010f56f
2 changed files with 10 additions and 0 deletions
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3
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -939,6 +939,7 @@ multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{31-27} = 0b1110; // non-predicated
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
let Inst{11-0} = imm;
@ -952,6 +953,7 @@ multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{31-27} = 0b1110; // non-predicated
let Inst{11-4} = 0b00000000;
let isCommutable = Commutable;
let Inst{3-0} = Rm;
@ -967,6 +969,7 @@ multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{31-27} = 0b1110; // non-predicated
let Inst{11-0} = shift;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;

7
llvm/test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -226,3 +226,10 @@
# CHECK: blx #60
0x0f 0x00 0x00 0xfa
# CHECK-NOT: adcs r10, r8, r0, asr #6
# CHECK: adcshi r10, r8, r0, asr #6
0x40 0xa3 0xb8 0x80
# CHECK: adcshi r10, r8, r0, asr r3
0x50 0xa3 0xb8 0x80