Add sanity checking for invalid register encodings for saturating instructions.
llvm-svn: 129096
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@ -1546,6 +1546,11 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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// A8.6.183 SSAT
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// if d == 15 || n == 15 then UNPREDICTABLE;
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if (decodeRd(insn) == 15 || decodeRm(insn) == 15)
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return false;
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const TargetInstrDesc &TID = ARMInsts[Opcode];
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NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
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@ -0,0 +1,11 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 0: 1: 0|
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# -------------------------------------------------------------------------------------------------
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#
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# A8.6.183 SSAT
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# if d == 15 || n == 15 then UNPREDICTABLE;
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0x1a 0xf4 0xa0 0xe6
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