Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
llvm-svn: 128940
This commit is contained in:
Owen Anderson
parent
0cb4acfc8d
commit
77aa266de8
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@ -55,7 +55,6 @@ namespace {
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void ExpandVLD(MachineBasicBlock::iterator &MBBI);
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void ExpandVST(MachineBasicBlock::iterator &MBBI);
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void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
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void ExpandSBitOp(MachineBasicBlock::iterator &MBBI);
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void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
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unsigned Opc, bool IsExt, unsigned NumRegs);
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void ExpandMOV32BitImm(MachineBasicBlock &MBB,
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@ -630,43 +629,6 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
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MI.eraseFromParent();
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}
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void ARMExpandPseudo::ExpandSBitOp(MachineBasicBlock::iterator &MBBI) {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock &MBB = *MI.getParent();
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unsigned OldOpc = MI.getOpcode();
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unsigned Opc = 0;
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switch (OldOpc) {
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case ARM::ADCSSrr:
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Opc = ARM::ADCrr;
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break;
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case ARM::ADCSSri:
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Opc = ARM::ADCri;
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break;
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case ARM::ADCSSrs:
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Opc = ARM::ADCrs;
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break;
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case ARM::SBCSSrr:
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Opc = ARM::SBCrr;
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break;
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case ARM::SBCSSri:
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Opc = ARM::SBCri;
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break;
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case ARM::SBCSSrs:
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Opc = ARM::SBCrs;
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break;
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default:
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llvm_unreachable("Unknown opcode?");
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}
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
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MIB.addOperand(MachineOperand::CreateImm(0)); // Predicate
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MIB.addOperand(MachineOperand::CreateImm(0)); // S bit
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for (unsigned i = 0; i < MI.getNumOperands(); ++i)
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MIB.addOperand(MI.getOperand(i));
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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}
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void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI) {
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MachineInstr &MI = *MBBI;
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@ -979,15 +941,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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ExpandMOV32BitImm(MBB, MBBI);
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return true;
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case ARM::ADCSSri:
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case ARM::ADCSSrr:
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case ARM::ADCSSrs:
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case ARM::SBCSSri:
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case ARM::SBCSSrr:
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case ARM::SBCSSrs:
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ExpandSBitOp(MBBI);
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return true;
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case ARM::VMOVQQ: {
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unsigned DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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@ -2390,7 +2390,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
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assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
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int index = ArgLocs[i].getValNo();
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// Some Ins[] entries become multiple ArgLoc[] entries.
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// Process them only once.
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if (index != lastInsIndex)
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@ -2966,7 +2966,7 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
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SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
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DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
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SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
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DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
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DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
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@ -4147,7 +4147,7 @@ static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
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&VTBLMask[0], 8));
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return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
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return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
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&VTBLMask[0], 8));
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}
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@ -4520,7 +4520,7 @@ static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
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DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
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}
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static SDValue
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static SDValue
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LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
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// Convert to float
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// float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
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@ -4531,7 +4531,7 @@ LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
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Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
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// Get reciprocal estimate.
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// float4 recip = vrecpeq_f32(yf);
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Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
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// Because char has a smaller range than uchar, we can actually get away
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// without any newton steps. This requires that we use a weird bias
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@ -4549,7 +4549,7 @@ LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
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return X;
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}
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static SDValue
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static SDValue
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LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
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SDValue N2;
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// Convert to float.
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@ -4559,13 +4559,13 @@ LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
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N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
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N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
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N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
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// Use reciprocal estimate and one refinement step.
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// float4 recip = vrecpeq_f32(yf);
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// recip *= vrecpsq_f32(yf, recip);
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N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
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N1, N2);
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N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
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@ -4595,15 +4595,15 @@ static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
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SDValue N0 = Op.getOperand(0);
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SDValue N1 = Op.getOperand(1);
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SDValue N2, N3;
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if (VT == MVT::v8i8) {
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N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
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N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
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N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
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DAG.getIntPtrConstant(4));
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N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
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DAG.getIntPtrConstant(4));
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DAG.getIntPtrConstant(4));
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N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
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DAG.getIntPtrConstant(0));
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N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
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@ -4614,7 +4614,7 @@ static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
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N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
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N0 = LowerCONCAT_VECTORS(N0, DAG);
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N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
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return N0;
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}
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@ -4630,32 +4630,32 @@ static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
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SDValue N0 = Op.getOperand(0);
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SDValue N1 = Op.getOperand(1);
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SDValue N2, N3;
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if (VT == MVT::v8i8) {
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N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
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N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
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N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
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DAG.getIntPtrConstant(4));
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N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
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DAG.getIntPtrConstant(4));
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DAG.getIntPtrConstant(4));
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N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
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DAG.getIntPtrConstant(0));
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N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
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DAG.getIntPtrConstant(0));
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N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
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N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
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N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
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N0 = LowerCONCAT_VECTORS(N0, DAG);
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N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
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N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
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DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
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N0);
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return N0;
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}
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// v4i16 sdiv ... Convert to float.
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// float4 yf = vcvt_f32_s32(vmovl_u16(y));
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// float4 xf = vcvt_f32_s32(vmovl_u16(x));
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@ -4668,13 +4668,13 @@ static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
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// float4 recip = vrecpeq_f32(yf);
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// recip *= vrecpsq_f32(yf, recip);
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// recip *= vrecpsq_f32(yf, recip);
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N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
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N1, N2);
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N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
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N1, N2);
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N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
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@ -5024,6 +5024,48 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
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case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
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case ARM::ADCSSri:
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case ARM::ADCSSrr:
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case ARM::ADCSSrs:
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case ARM::SBCSSri:
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case ARM::SBCSSrr:
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case ARM::SBCSSrs: {
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unsigned OldOpc = MI->getOpcode();
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unsigned Opc = 0;
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switch (OldOpc) {
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case ARM::ADCSSrr:
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Opc = ARM::ADCrr;
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break;
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case ARM::ADCSSri:
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Opc = ARM::ADCri;
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break;
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case ARM::ADCSSrs:
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Opc = ARM::ADCrs;
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break;
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case ARM::SBCSSrr:
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Opc = ARM::SBCrr;
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break;
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case ARM::SBCSSri:
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Opc = ARM::SBCri;
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break;
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case ARM::SBCSSrs:
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Opc = ARM::SBCrs;
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break;
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default:
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llvm_unreachable("Unknown opcode?");
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}
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MachineInstrBuilder MIB =
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BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(Opc));
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for (unsigned i = 0; i < MI->getNumOperands(); ++i)
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MIB.addOperand(MI->getOperand(i));
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AddDefaultPred(MIB);
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MIB.addReg(ARM::CPSR, RegState::Define); // S bit
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MI->eraseFromParent();
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return BB;
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}
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case ARM::tMOVCCr_pseudo: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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@ -5326,7 +5368,7 @@ static SDValue PerformMULCombine(SDNode *N,
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static SDValue PerformANDCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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// Attempt to use immediate-form VBIC
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BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
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DebugLoc dl = N->getDebugLoc();
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@ -5851,7 +5893,7 @@ static SDValue CombineBaseUpdate(SDNode *N,
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EVT VecTy;
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if (isLoad)
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VecTy = N->getValueType(0);
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else
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else
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VecTy = N->getOperand(AddrOpIdx+1).getValueType();
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unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
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if (isLaneOp)
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@ -5901,7 +5943,7 @@ static SDValue CombineBaseUpdate(SDNode *N,
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DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
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break;
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}
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}
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return SDValue();
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}
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@ -936,8 +936,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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}
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// Carry setting variants
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
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def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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Size4Bytes, IIC_iALUi,
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[(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
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@ -2197,10 +2196,12 @@ defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
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BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
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// ADC and SUBC with 's' bit set.
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defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
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BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
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defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
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BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
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let usesCustomInserter = 1 in {
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defm ADCS : AI1_adde_sube_s_irs<
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BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
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defm SBCS : AI1_adde_sube_s_irs<
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BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
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}
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def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
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IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
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