98ebcd88f2
* In the F3_1 class, default asi to 0 because it's not currently used
...
* In the F3_3 class, remove mention of asi because it's not part of the format
llvm-svn: 16999
2004-10-14 21:53:39 +00:00
1f864b5583
Add FSTOI, FDTOI (fp to integer cast) instructions.
...
llvm-svn: 16996
2004-10-14 19:39:35 +00:00
1519c24cff
Rewrite emitCastOperation, refactoring parts of it into emitIntegerCast, and
...
adding emitFPToIntegerCast.
llvm-svn: 16995
2004-10-14 19:39:34 +00:00
38a4dd3d15
Add list of libc procedures we'll use, at some point.
...
Update list of currently failing tests.
ADJCALLSTACK* support is done.
llvm-svn: 16994
2004-10-14 19:39:33 +00:00
1f596c3358
* Claim to support machine code emission - return false from
...
addPassesToEmitMachineCode()
* Add support for registers and constants in getMachineOpValue()
This enables running "int main() { ret 0 }" via the PowerPC JIT.
llvm-svn: 16983
2004-10-14 06:39:56 +00:00
8b1bf4323f
* Include the real (generated) version of getBinaryCodeForInstr()
...
* Add implementation of getMachineOpValue() for generated code emitter
* Convert assert()s in unimplemented functions to abort()s so that non-debug
builds fail predictably
* Add file header comments
llvm-svn: 16981
2004-10-14 06:07:25 +00:00
c2d6aaeaa0
* Make a PPC32-specific code emitter because we have separate classes for 32-
...
and 64-bit code emitters that cannot share code unless we use virtual
functions
* Identify components being built by tablegen with more detail by assigning them
to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building
PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64
llvm-svn: 16980
2004-10-14 06:04:56 +00:00
d38a7605d8
Checking in code that works on my simple test case. However, there is still a bug with branches that I need to fix.
...
llvm-svn: 16979
2004-10-14 06:04:28 +00:00
189f3dc8d2
There is only one field in an instruction, and that is `Inst', the final view of
...
the instruction binary format, all others are simply operands and should not
have the `field' label
llvm-svn: 16978
2004-10-14 05:55:37 +00:00
d6ac8f5e5a
PowerPC instruction definitions use LittleEndian-style encoding [0..31]
...
llvm-svn: 16977
2004-10-14 05:54:38 +00:00
dba1f62eb8
Add isLittleEndianEncoding to InstrInfo class, defaults to `off'
...
llvm-svn: 16976
2004-10-14 05:53:40 +00:00
ace94df71f
Update to reflect changes in Makefile rules.
...
llvm-svn: 16950
2004-10-13 11:46:52 +00:00
58043a1473
Fix a warning that is emitted on the suns
...
llvm-svn: 16917
2004-10-11 15:50:40 +00:00
b4cb9fc7c9
Add ModuloScheduling to the recursive build tree
...
llvm-svn: 16905
2004-10-10 23:36:09 +00:00
9da1134bfb
Adjust header file inclusion due to move
...
llvm-svn: 16904
2004-10-10 23:34:50 +00:00
c70014bea3
Adjust comment header and paths to refect move
...
llvm-svn: 16903
2004-10-10 23:34:36 +00:00
4a4af7e20c
ModuloScheduling moved to lib/Target/SparcV9 as it is SparcV9-specific
...
llvm-svn: 16902
2004-10-10 23:33:20 +00:00
823f302ff9
Initial version of automake Makefile.am file.
...
llvm-svn: 16898
2004-10-10 22:52:14 +00:00
ef6ba8db70
Add the new InstrSched directory.
...
llvm-svn: 16897
2004-10-10 22:51:03 +00:00
97327f05fc
Initial version of automake Makefile.am file.
...
llvm-svn: 16893
2004-10-10 22:20:40 +00:00
4a69c9d667
Fix assertion failure when calling or returning from a function which
...
returns 'bool' type.
llvm-svn: 16884
2004-10-10 20:34:17 +00:00
7be91b34b8
Implement eliminateCallFramePseudoInstr().
...
Wrap a long comment line.
llvm-svn: 16883
2004-10-10 19:57:21 +00:00
9770e416c5
Model calls as *both* using *and* killing O0..O5, because callees use the
...
argument values passed in (so they're not dead until *after* the call),
and callees are free to modify those registers.
llvm-svn: 16882
2004-10-10 19:57:20 +00:00
8a4d5caa76
Fix whitespace and wrap some long lines.
...
Deal with allocating stack space for outgoing args and copying them into the
correct stack slots (at least, we can copy <=32-bit int args).
We now correctly generate ADJCALLSTACK* instructions.
llvm-svn: 16881
2004-10-10 19:57:18 +00:00
3acdb7fa1b
bling bling!
...
llvm-svn: 16873
2004-10-10 16:26:13 +00:00
f9ae6db749
Instead of silently breaking, print notification of why this doesn't work.
...
llvm-svn: 16870
2004-10-09 21:13:51 +00:00
74584cd842
update according to tonight's info
...
llvm-svn: 16866
2004-10-09 05:58:27 +00:00
9c0710781d
Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the
...
default 32/BE target on sparc hosts, and ppc will continue to be the default
on other hosts.
llvm-svn: 16865
2004-10-09 05:57:01 +00:00
23c8d0b65a
The person who was planning to add SSE support isn't anymore, so disable
...
the -sse* options (to avoid misleading people).
Also, the stack alignment of the target doesn't depend on whether SSE is
eventually implemented, so remove a comment.
llvm-svn: 16860
2004-10-08 22:41:46 +00:00
97ea4206f7
Fix a major regression from the bugfix for 2004-10-08-SelectSetCCFold.llx,
...
which prevented setcc's from being folded into branches. It appears that
conditional branchinst's CC operand is actually operand(2), not operand(0)
as we might expect. :(
llvm-svn: 16859
2004-10-08 22:24:31 +00:00
e4e1360eab
Adjust paths due to moving InstrSched to lib/Target/SparcV9
...
llvm-svn: 16852
2004-10-08 18:30:22 +00:00
24eb38af7c
InstrSched is SparcV9-specific and so has been moved to lib/Target/SparcV9/
...
llvm-svn: 16849
2004-10-08 18:12:14 +00:00
5a9976ac29
Single-space instead of double-spacing in the Makefile
...
llvm-svn: 16848
2004-10-08 18:11:14 +00:00
e75c26687c
Build InstrSched as well, and all three subdirs can be built independently
...
llvm-svn: 16847
2004-10-08 18:10:48 +00:00
0be2f50401
Fix bug: 2004-10-08-SelectSetCCFold.llx. Normally this is hidden by the
...
instcombine xform, which is why we didn't notice it before.
llvm-svn: 16840
2004-10-08 16:34:13 +00:00
b58dd6799f
Implement logical and with an immediate that consists of a contiguous block
...
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.
int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }
_andn4:
rlwinm r3, r3, 0, 0, 29
blr
_clearhi:
rlwinm r3, r3, 0, 16, 31
blr
_clearlo:
rlwinm r3, r3, 0, 0, 15
blr
_clearmid:
rlwinm r3, r3, 0, 8, 23
blr
_clearwrap:
rlwinm r3, r3, 0, 24, 7
blr
llvm-svn: 16832
2004-10-08 02:49:24 +00:00
6e6514c47e
Several fixes and enhancements to the PPC32 backend.
...
1. Fix an illegal argument to getClassB when deciding whether or not to
sign extend a byte load.
2. Initial addition of isLoad and isStore flags to the instruction .td file
for eventual use in a scheduler.
3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
that we can emit the PowerPC shifted immediate instructions far more
often. This allows us to emit the following code:
int foo(int x) { return x | 0x00F0000; }
_foo:
.LBB_foo_0: ; entry
; IMPLICIT_DEF
oris r3, r3, 15
blr
llvm-svn: 16826
2004-10-07 22:30:03 +00:00
c6b63cd2ed
Add ori reg, reg, 0 as a move instruction. This can be generated from
...
loading a 32bit constant into a register whose low halfword is all zeroes.
We now omit the ori after the lis for the following C code:
int bar(int y) { return y * 0x00F0000; }
_bar:
.LBB_bar_0: ; entry
; IMPLICIT_DEF
lis r2, 15
mullw r3, r3, r2
blr
llvm-svn: 16825
2004-10-07 22:26:12 +00:00
70a9d9c0b1
Remove unnecessary header include
...
llvm-svn: 16824
2004-10-07 22:24:32 +00:00
f94f985bbd
Correct some typeos
...
llvm-svn: 16770
2004-10-06 16:28:24 +00:00
93867e516a
Remove debugging code, fix encoding problem. This fixes the problems
...
the JIT had last night.
llvm-svn: 16766
2004-10-06 14:31:50 +00:00
9a1fbaf1e9
Turning on fsel code gen now that we can do so would be good.
...
llvm-svn: 16765
2004-10-06 11:03:30 +00:00
fac8529df8
Implement floating point select for lt, gt, le, ge using the powerpc fsel
...
instruction.
Now, rather than emitting the following loop out of bisect:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f4
bge .LBB_main_64 ; no_exit.0.i
.LBB_main_63: ; no_exit.0.i
b .LBB_main_65 ; no_exit.0.i
.LBB_main_64: ; no_exit.0.i
fmr f2, f1
.LBB_main_65: ; no_exit.0.i
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f5
bge .LBB_main_67 ; no_exit.0.i
.LBB_main_66: ; no_exit.0.i
b .LBB_main_68 ; no_exit.0.i
.LBB_main_67: ; no_exit.0.i
fmr f4, f1
.LBB_main_68: ; no_exit.0.i
fadd f1, f2, f4
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fcmpu cr0, f4, f0
bgt .LBB_main_70 ; no_exit.0.i
.LBB_main_69: ; no_exit.0.i
b .LBB_main_71 ; no_exit.0.i
.LBB_main_70: ; no_exit.0.i
fmr f0, f4
.LBB_main_71: ; no_exit.0.i
fsub f1, f2, f1
addi r2, r2, -1
fcmpu cr0, f1, f3
blt .LBB_main_73 ; no_exit.0.i
.LBB_main_72: ; no_exit.0.i
b .LBB_main_74 ; no_exit.0.i
.LBB_main_73: ; no_exit.0.i
fmr f3, f1
.LBB_main_74: ; no_exit.0.i
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
We emit this instead:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
fsel f1, f1, f1, f2
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f2, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f2
fsel f2, f2, f2, f4
fadd f1, f1, f2
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fsub f5, f0, f4
fsel f0, f5, f0, f4
fsub f1, f2, f1
addi r2, r2, -1
fsub f2, f1, f3
fsel f3, f2, f3, f1
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
llvm-svn: 16764
2004-10-06 09:53:04 +00:00
6835dedb5b
Codegen signed mod by 2 or -2 more efficiently. Instead of generating:
...
t:
mov %EDX, DWORD PTR [%ESP + 4]
mov %ECX, 2
mov %EAX, %EDX
sar %EDX, 31
idiv %ECX
mov %EAX, %EDX
ret
Generate:
t:
mov %ECX, DWORD PTR [%ESP + 4]
*** mov %EAX, %ECX
cdq
and %ECX, 1
xor %ECX, %EDX
sub %ECX, %EDX
*** mov %EAX, %ECX
ret
Note that the two marked moves are redundant, and should be eliminated by the
register allocator, but aren't.
Compare this to GCC, which generates:
t:
mov %eax, DWORD PTR [%esp+4]
mov %edx, %eax
shr %edx, 31
lea %ecx, [%edx+%eax]
and %ecx, -2
sub %eax, %ecx
ret
or ICC 8.0, which generates:
t:
movl 4(%esp), %ecx #3.5
movl $-2147483647, %eax #3.25
imull %ecx #3.25
movl %ecx, %eax #3.25
sarl $31, %eax #3.25
addl %ecx, %edx #3.25
subl %edx, %eax #3.25
addl %eax, %eax #3.25
negl %eax #3.25
subl %eax, %ecx #3.25
movl %ecx, %eax #3.25
ret #3.25
We would be in great shape if not for the moves.
llvm-svn: 16763
2004-10-06 05:01:07 +00:00
e4c60eb704
Really fix FreeBSD, which apparently doesn't tolerate the extern.
...
Thanks to Jeff Cohen for pointing out my goof.
llvm-svn: 16762
2004-10-06 04:21:52 +00:00
7bd8f1332d
Fix a scary bug with signed division by a power of two. We used to generate:
...
s: ;; X / 4
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, %EAX
sar %ECX, 1
shr %ECX, 30
mov %EDX, %EAX
add %EDX, %ECX
sar %EAX, 2
ret
When we really meant:
s:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, %EAX
sar %ECX, 1
shr %ECX, 30
add %EAX, %ECX
sar %EAX, 2
ret
Hey, this also reduces register pressure too :)
llvm-svn: 16761
2004-10-06 04:19:43 +00:00
147edd2f7e
Codegen signed divides by 2 and -2 more efficiently. In particular
...
instead of:
s: ;; X / 2
movl 4(%esp), %eax
movl %eax, %ecx
shrl $31, %ecx
movl %eax, %edx
addl %ecx, %edx
sarl $1, %eax
ret
t: ;; X / -2
movl 4(%esp), %eax
movl %eax, %ecx
shrl $31, %ecx
movl %eax, %edx
addl %ecx, %edx
sarl $1, %eax
negl %eax
ret
Emit:
s:
movl 4(%esp), %eax
cmpl $-2147483648, %eax
sbbl $-1, %eax
sarl $1, %eax
ret
t:
movl 4(%esp), %eax
cmpl $-2147483648, %eax
sbbl $-1, %eax
sarl $1, %eax
negl %eax
ret
llvm-svn: 16760
2004-10-06 04:02:39 +00:00
e9bfa5a2a4
Add some new instructions. Fix the asm string for sbb32rr
...
llvm-svn: 16759
2004-10-06 04:01:02 +00:00
32ed828f46
FreeBSD uses GCC. Patch contributed by Jeff Cohen!
...
llvm-svn: 16756
2004-10-06 03:15:44 +00:00
d1ab378be5
* Prune #includes
...
* Update comments
* Rearrange code a bit
* Finally ELIMINATE the GAS workaround emitter for Intel mode. woot!
llvm-svn: 16647
2004-10-04 07:31:08 +00:00
68ab0beb1b
Add support for emitting AT&T style .s files, and make it the default. Users
...
may now choose their output format with the -x86-asm-syntax={intel|att} flag.
llvm-svn: 16646
2004-10-04 07:24:48 +00:00
8bbde2fb33
Convert some missed patterns to support AT&T style
...
llvm-svn: 16645
2004-10-04 07:23:07 +00:00
2e99778aad
Apparently the GNU assembler has a HUGE hack to be compatible with really
...
old and broken AT&T syntax assemblers. The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.
llvm-svn: 16644
2004-10-04 07:08:46 +00:00
af69503332
Fix incorrect suffix
...
llvm-svn: 16642
2004-10-04 05:20:16 +00:00
e1a2826d51
Fix some more missed suffixes and swapped operands
...
llvm-svn: 16641
2004-10-04 01:38:10 +00:00
a488f04f3e
Add missing suffixes to FP instructions for AT&T mode
...
llvm-svn: 16640
2004-10-04 00:43:31 +00:00
5683260187
Add support for the -x86-asm-syntax flag, which can be used to choose between
...
Intel and AT&T style assembly language. The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.
llvm-svn: 16639
2004-10-03 20:36:57 +00:00
4e59a14909
Add support to the instruction patterns for AT&T style output, which will
...
hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also
includes changes to wrap the whole file to 80 columns! Woot! :)
Note that the AT&T style output has not been tested at all.
llvm-svn: 16638
2004-10-03 20:35:00 +00:00
42c43b2cb3
Add initial support for variants
...
llvm-svn: 16635
2004-10-03 19:34:18 +00:00
dd9bb500ad
Make EmitMappingInfo into an "external location" option, so that it can be set
...
or cleared externally.
llvm-svn: 16623
2004-09-30 20:20:01 +00:00
a1640d2427
I think this will handle double args.
...
llvm-svn: 16618
2004-09-30 19:44:32 +00:00
7efd5fcb3a
Mark the instructions that have delay slots with the hasDelaySlot flag.
...
Add some comments.
llvm-svn: 16611
2004-09-30 04:04:48 +00:00
1f48ef2a9a
Use TargetMachine::hasDelaySlot() instead of our old switch statement
...
to find instrs that have delay slots.
llvm-svn: 16610
2004-09-30 04:04:47 +00:00
4592f86ef1
Change the #ifdefs to allow compilation with a V8 compiler, but the JIT still
...
won't work if not compiled in V9 mode, currently by GCC only, because Sun's
system compiler does not tell us if it's a V8 or V9 system.
llvm-svn: 16602
2004-09-29 23:01:17 +00:00
fb1fd0cb5f
Update list of shootout programs that should be working.
...
llvm-svn: 16595
2004-09-29 20:45:06 +00:00
ede068a8d3
Tell the target description that calls clobber registers O0...O5.
...
llvm-svn: 16594
2004-09-29 20:45:05 +00:00
3a340dd7cd
FITOD is spelled "fitod", not "fitos". Ouch.
...
llvm-svn: 16591
2004-09-29 19:59:07 +00:00
47095da661
Don't use .quad to output double constants. The assembler must have a bug or
...
something, because the wrong bit patterns get output.
llvm-svn: 16590
2004-09-29 19:59:06 +00:00
81f5e08573
Recognize FpMOVD as a move.
...
llvm-svn: 16586
2004-09-29 16:45:47 +00:00
2f1d0ae95e
Generate better code by being far less clever when it comes to the select instruction. Don't create overlapping register lifetimes
...
llvm-svn: 16580
2004-09-29 05:00:31 +00:00
c44da15813
add results
...
llvm-svn: 16579
2004-09-29 03:48:55 +00:00
7b6df6def2
improve Type::BoolTy codegen by eliminating unnecessary clears and sign extends
...
llvm-svn: 16578
2004-09-29 03:45:33 +00:00
4023d4e191
Simplify copyConstantToRegister() for longs, using a pair of recursive calls.
...
Copy constant-pool entries' addresses into registers before loading out of them,
to avoid errors from the assembler.
Handle loading call args past the 6th one off the stack.
Add IMPLICIT_DEF pseudo-instrs for double and long arguments passed in register
pairs.
Use FpMOVD to copy doubles around instead of the horrible store-load thing we
were doing before.
Handle 'ret double' and 'ret long'.
Fix a bug in handling 'and/or/xor long'.
llvm-svn: 16577
2004-09-29 03:34:41 +00:00
eae5b17dba
Fix bug recognizing moves: isMoveInstr should only treat ORs with %g0 as
...
moves, not all ORs.
llvm-svn: 16576
2004-09-29 03:28:15 +00:00
069bb989e4
Use FpMOVD pseudo-instruction to move doubles around.
...
llvm-svn: 16575
2004-09-29 03:27:30 +00:00
da371d9cf3
Add new FpMOVD pseudo-instruction, used to move doubles around.
...
llvm-svn: 16574
2004-09-29 03:27:29 +00:00
7f11dd4825
Fix double and long alignment.
...
Call the FPMover pass after register allocation.
llvm-svn: 16573
2004-09-29 03:26:27 +00:00
ead8e39832
Put quotes around argument to .section directive.
...
llvm-svn: 16572
2004-09-29 03:25:40 +00:00
457180c597
Add createSparcV8FPMoverPass().
...
llvm-svn: 16571
2004-09-29 03:25:39 +00:00
ce0ba4857b
Pass which converts FpMOVD (double move pseudoinstructions) to pairs
...
of FMOVS instrs.
llvm-svn: 16570
2004-09-29 03:24:34 +00:00
26566f0b68
To go along with sabre's improved InstCombining, improve recognition of
...
integers that we can use as immediate values in instructions.
Example from yacr2:
- lis r10, -1
- ori r10, r10, 65535
- add r28, r28, r10
+ addi r28, r28, -1
addi r7, r7, 1
addi r9, r9, 1
b .LBB_main_9 ; loopentry.1.i214
llvm-svn: 16566
2004-09-29 02:35:05 +00:00
c762ab723b
Add support for the isLoad and isStore flags, needed by the instruction scheduler
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llvm-svn: 16555
2004-09-28 21:29:00 +00:00
6652223bd6
Capture delay slot info
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llvm-svn: 16551
2004-09-28 18:34:14 +00:00
6280a7b716
Since we use alloca now make sure we include the proper headers for it.
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llvm-svn: 16536
2004-09-28 02:53:15 +00:00
edbb20cf7f
Use alloca instead of a C99 style array. This should fix the
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compilation problem in windows.
llvm-svn: 16535
2004-09-28 02:47:38 +00:00
3ce42ec7ee
Pull assignment out of for loop conditional in order for this to
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compile under windows. Patch contributed by Paolo Invernizzi!
llvm-svn: 16534
2004-09-28 02:40:37 +00:00
d409d38151
SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!
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llvm-svn: 16526
2004-09-27 18:22:18 +00:00
8656a156cf
Correct some BuildMI arguments for the upcoming simple scheduler
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llvm-svn: 16519
2004-09-27 05:08:17 +00:00
a68d76ebfa
Fix the copy-pasto that Brian noticed: V8 int regs are 32-bits wide, not 64.
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llvm-svn: 16518
2004-09-26 21:07:43 +00:00
49cf74b26c
Fix the last of the major PPC GEP folding deficiencies. This will allow
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the ISel to use indexed and non-zero immediate offsets for GEPs that have
more than one use. This is common for instruction sequences such as a load
followed by a modify and store to the same address.
llvm-svn: 16493
2004-09-23 05:31:33 +00:00
379a05b52a
Use the V8/V9 shared register file description
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llvm-svn: 16485
2004-09-22 21:48:50 +00:00
3c08658d56
Combine the F2 and F3 instruction classes into one file for simplicity
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llvm-svn: 16484
2004-09-22 21:38:42 +00:00
efce1ef9c3
Fix file header path
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llvm-svn: 16483
2004-09-22 21:29:12 +00:00
009aaf9968
Prettify formatting of the file, adjust paths to making V8 a subdir of Sparc
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llvm-svn: 16482
2004-09-22 20:09:29 +00:00
d55f854a5d
V8 is now a subdirectory of Sparc; adjust paths accordingly
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llvm-svn: 16481
2004-09-22 20:08:52 +00:00
033b816171
add optimized code sequences for setcc x, 0
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llvm-svn: 16478
2004-09-22 04:40:25 +00:00
89dd63733a
The real x87 floating point registers should not be allocatable. They
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are only used by the stackifier when transforming FPn register
allocations to the real stack file x87 registers.
llvm-svn: 16472
2004-09-21 21:22:11 +00:00
6b17bf7193
s/ISel/PPC64ISel/ to have unique class names for debugging via gdb because the
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C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16471
2004-09-21 18:22:33 +00:00
87201ce8f9
s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because the
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C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16470
2004-09-21 18:22:19 +00:00
43bd39e04e
s/ISel/X86ISel/ to have unique class names for debugging via gdb because the C++
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front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16469
2004-09-21 18:21:21 +00:00
0f28cce60c
Make sure to set the operand list
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llvm-svn: 16466
2004-09-21 17:30:54 +00:00
4f2cf030e8
'Pass' should now not be derived from by clients. Instead, they should derive
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from ModulePass. Instead of implementing Pass::run, then should implement
ModulePass::runOnModule.
llvm-svn: 16436
2004-09-20 04:48:05 +00:00
6614946443
Convert code to compile with vc7.1.
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Patch contributed by Paolo Invernizzi. Thanks Paolo!
llvm-svn: 16368
2004-09-15 17:06:42 +00:00
4bf01357e1
Fit long lines into 80 cols via creative space elimination
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llvm-svn: 16353
2004-09-15 01:40:18 +00:00
2d01db846b
Targets are independent of each other, so compile them in parallel
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llvm-svn: 16351
2004-09-15 01:34:25 +00:00
e8e81a2941
Revamp the Register class, and allow the use of the RegisterGroup class to
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specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
llvm-svn: 16330
2004-09-14 04:17:02 +00:00
247c29e4b0
Changes to make this work with Jason's patch. I checked this by hand, but
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would appreciate if others would also look at this to make sure I didn't
botch something obvious
llvm-svn: 16312
2004-09-13 21:32:03 +00:00
72be9ae024
Fix filename: Printer.cpp has become X86AsmPrinter.cpp
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llvm-svn: 16299
2004-09-12 21:26:04 +00:00
04bbe6fa25
Renamed file to SparcV8ISelSimple.cpp
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llvm-svn: 16267
2004-09-10 18:51:12 +00:00
86584749b6
Roll back constant printing changes until the problems with larger
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programs and C++ can be looked at in detail.
llvm-svn: 16266
2004-09-10 18:01:45 +00:00
371403193c
Use a shorter form to express implicit use/defs in FpGETRESULT and
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FpSETRESULT.
llvm-svn: 16247
2004-09-08 18:29:31 +00:00
8b700215ed
A call instruction should implicitely define ST0 since the return
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value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.
llvm-svn: 16246
2004-09-08 16:54:54 +00:00
acafb39cc3
This file does not need <iostream>, I think.
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llvm-svn: 16245
2004-09-08 04:10:52 +00:00
54bcf2db01
Add 64 bit divide instructions, and use them
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llvm-svn: 16198
2004-09-06 18:46:59 +00:00
175fdd4678
* Change PPC32AsmPrinter => PowerPCAsmPrinter since it is now shared between
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Darwin and AIX and is not 32- or 64-bit specific
* Bring back PowerPC.td as a result, to make it use the `PowerPC' class name
* Adjust Makefile accordingly
llvm-svn: 16174
2004-09-05 02:42:44 +00:00
4acadb3af7
Renamed PPC32AsmPrinter.cpp => PowerPCAsmPrinter.cpp as the Darwin and AIX asm
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printers are now unified into one file.
llvm-svn: 16173
2004-09-05 02:27:37 +00:00
4d847047a0
Include MathExtras.h to fix build breakage, thanks to Vladimir
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llvm-svn: 16164
2004-09-04 14:51:26 +00:00
4bfceb1ed5
All PPC instructions are now auto-printed
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32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out
llvm-svn: 16163
2004-09-04 05:00:00 +00:00
0ded30aec4
Clean up some "clean:" targets so they use $(VERB) and don't print anything
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by default, like every other "clean" target in LLVM.
llvm-svn: 16161
2004-09-03 23:19:53 +00:00
6173878304
Convert remaining X-Form and Pseudo instructions over to asm writer
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llvm-svn: 16142
2004-09-02 08:13:00 +00:00
c6e81f0fde
Back to compiling land for v8
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llvm-svn: 16138
2004-09-02 02:37:43 +00:00
7c16caa336
Changes For Bug 352
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Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
a113d74e4c
convert M and MD form instructions to generated asm writer
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llvm-svn: 16121
2004-08-31 02:28:08 +00:00
143cf94f92
Move yet more instructions over to being printed by the generated asm writer
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llvm-svn: 16112
2004-08-30 02:28:06 +00:00
8aca0b494d
Reduce the number of arguments in the instruction builder and make some
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improvements on instruction selection that account for register and frame
index bases.
Patch contributed by Jeff Cohen. Thanks Jeff!
llvm-svn: 16110
2004-08-30 00:13:26 +00:00
6cdbd22245
Convert A-Form instructions to auto-generated asm writer
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llvm-svn: 16107
2004-08-29 22:45:13 +00:00
434234f6d1
Register sizes should be specified in bits
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llvm-svn: 16106
2004-08-29 22:03:40 +00:00
8cb6bd5f3c
Improvements to int->float cast code for PPC-64
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llvm-svn: 16105
2004-08-29 22:02:43 +00:00
4483df8b63
Implement the following missing functionality in the PPC backend:
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cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite. Fixes Regression/casts
llvm-svn: 16081
2004-08-29 08:19:32 +00:00
fa2bf42539
Register sizes are in bits, not bytes
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llvm-svn: 16070
2004-08-27 04:28:10 +00:00
8b5b3fdb50
Add getAllocatableSet() function.
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llvm-svn: 16059
2004-08-26 22:21:04 +00:00
7f00753f70
Previous checkin broke printf(%a) support for fp constants-- re-fix it.
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llvm-svn: 16051
2004-08-25 19:37:26 +00:00
35eb7aeae3
New version of Bill Wendling's PR33 patch.
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llvm-svn: 16050
2004-08-25 19:00:42 +00:00
dfa9dbceaa
Add -sse[,2,3] arguments to LLC
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llvm-svn: 16018
2004-08-24 08:18:44 +00:00
61e6dbc761
Nuke commented out stuff
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llvm-svn: 16017
2004-08-24 08:18:27 +00:00
75dca84c7f
This code is dodgy, but the guaranteed assertion failure doesn't help anything.
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llvm-svn: 16014
2004-08-24 06:41:40 +00:00
98aa7797c3
Fix bug in PhyRegAlloc::setCallInterferences() handling call through a
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null pointer.
llvm-svn: 16013
2004-08-24 06:41:39 +00:00
d315f43587
Revise head-of-file comment.
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Eliminate some excess whitespace.
Fix bug in CallArgsDescriptor::get() handling call through a null pointer.
llvm-svn: 16012
2004-08-24 06:41:38 +00:00
1c57b4fa32
Kill a majority of unnecessary sign extensions for byte loads
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llvm-svn: 15991
2004-08-22 08:10:15 +00:00
64ef0262bd
Don't hard code the offset of the saved R31 in functions with frame pointers
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llvm-svn: 15990
2004-08-22 08:09:17 +00:00
45b0b7cd7c
Back out branchless SetCC code. While it helped a lot in some cases, it
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hurt a lot in others. Instead, improve branching version of SetCC and
Select instructions. The old code will be in CVS should we ever need to
dig it up again.
llvm-svn: 15979
2004-08-21 20:42:14 +00:00
70efc8f8e1
Switch from bytes to bits for alignment.
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Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit
llvm-svn: 15975
2004-08-21 20:14:40 +00:00
5f6556da45
Switch from bytes to bits for alignment for consistency
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llvm-svn: 15974
2004-08-21 20:14:13 +00:00
7c98308013
Reduce uses of getRegClass
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llvm-svn: 15973
2004-08-21 20:13:52 +00:00
a440d5b081
Convert regclass alignment from bytes to bites
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llvm-svn: 15972
2004-08-21 20:13:09 +00:00
b7ddc73b45
Convert bytes to bits in alignment
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llvm-svn: 15971
2004-08-21 20:09:46 +00:00
c1ba9fb6e1
Reduce uses of getRegClass
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llvm-svn: 15968
2004-08-21 19:51:17 +00:00
f7833ba375
Fix warning
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llvm-svn: 15964
2004-08-21 19:11:03 +00:00
3ad3ad4f3f
Move XForm instructions over to the auto-generated asm writer
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llvm-svn: 15962
2004-08-21 05:56:39 +00:00
6a92fdef72
Add two values
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llvm-svn: 15959
2004-08-21 02:17:39 +00:00
Misha Brukman