Fix some more missed suffixes and swapped operands
llvm-svn: 16641
This commit is contained in:
Chris Lattner
parent
a488f04f3e
commit
e1a2826d51
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@ -747,11 +747,11 @@ let isTwoAddress = 0 in {
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// Shift instructions
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// FIXME: provide shorter instructions when imm8 == 1
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def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
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"shl{b} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
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"shl{w} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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"shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
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"shl{l} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
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"shl{b} {$src2, $dst|$dst, $src2}">;
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def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
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@ -761,11 +761,11 @@ def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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let isTwoAddress = 0 in {
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def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
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"shl{b} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
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"shl{w} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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"shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
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"shl{l} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
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"shl{b} {$src, $dst|$dst, $src}">;
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def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
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@ -775,11 +775,11 @@ let isTwoAddress = 0 in {
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}
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def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
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"shr{b} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
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"shr{w} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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"shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
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"shr{l} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
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"shr{b} {$src2, $dst|$dst, $src2}">;
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@ -790,11 +790,11 @@ def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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let isTwoAddress = 0 in {
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def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
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"shr{b} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
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"shr{w} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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"shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
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"shr{l} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
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"shr{b} {$src, $dst|$dst, $src}">;
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def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
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@ -804,11 +804,11 @@ let isTwoAddress = 0 in {
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}
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def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
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"sar{b} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
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"sar{w} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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"sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
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"sar{l} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
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"sar{b} {$src2, $dst|$dst, $src2}">;
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@ -818,11 +818,11 @@ def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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"sar{l} {$src2, $dst|$dst, $src2}">;
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let isTwoAddress = 0 in {
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def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
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"sar{b} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
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"sar{w} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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"sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
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"sar{l} {%CL, $dst|$dst, %CL}">, Imp<[CL],[]>;
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"sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
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"sar{b} {$src, $dst|$dst, $src}">;
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def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
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@ -832,10 +832,10 @@ let isTwoAddress = 0 in {
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}
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def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
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"shld{l} {%CL, $src2, $dst|$dst, $src2, %CL}">,
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"shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
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Imp<[CL],[]>, TB;
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def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
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"shrd{l} {%CL, $src2, $dst|$dst, $src2, %CL}">,
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"shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
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Imp<[CL],[]>, TB;
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def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
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(ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
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@ -846,10 +846,10 @@ def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
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let isTwoAddress = 0 in {
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def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
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"shld{l} {%CL, $src2, $dst|$dst, $src2, %CL}">,
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"shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
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Imp<[CL],[]>, TB;
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def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
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"shrd{l} {%CL, $src2, $dst|$dst, $src2, %CL}">,
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"shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
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Imp<[CL],[]>, TB;
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def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
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(ops i32mem:$dst, R32:$src2, i8imm:$src3),
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@ -1043,18 +1043,24 @@ def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
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def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
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"test{l} {$src2, $src1|$src1, $src2}">;
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def TEST8ri : Ii8 <0xF6, MRM0r, (ops R8:$dst, i8imm:$src),
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"test{b} $dst, $src">; // flags = R8 & imm8
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def TEST16ri : Ii16<0xF7, MRM0r, (ops R16:$dst, i16imm:$src),
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"test{w} $dst, $src">, OpSize; // flags = R16 & imm16
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def TEST32ri : Ii32<0xF7, MRM0r, (ops R32:$dst, i32imm:$src),
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"test{l} $dst, $src">; // flags = R32 & imm32
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def TEST8mi : Ii8 <0xF6, MRM0m, (ops i32mem:$dst, i8imm:$src),
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"test{b} $dst, $src">; // flags = [mem8] & imm8
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def TEST16mi : Ii16<0xF7, MRM0m, (ops i16mem:$dst, i16imm:$src),
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"test{w} $dst, $src">, OpSize; // flags = [mem16] & imm16
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def TEST32mi : Ii32<0xF7, MRM0m, (ops i32mem:$dst, i32imm:$src),
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"test{l} $dst, $src">; // flags = [mem32] & imm32
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def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
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(ops R8:$src1, i8imm:$src2),
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"test{b} {$src2, $src1|$src1, $src2}">;
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def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
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(ops R16:$src1, i16imm:$src2),
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"test{w} {$src2, $src1|$src1, $src2}">, OpSize;
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def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
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(ops R32:$src1, i32imm:$src2),
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"test{l} {$src2, $src1|$src1, $src2}">;
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def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
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(ops i32mem:$src1, i8imm:$src2),
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"test{b} {$src2, $src1|$src1, $src2}">;
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def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
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(ops i16mem:$src1, i16imm:$src2),
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"test{w} {$src2, $src1|$src1, $src2}">, OpSize;
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def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
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(ops i32mem:$src1, i32imm:$src2),
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"test{l} {$src2, $src1|$src1, $src2}">;
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