Move yet more instructions over to being printed by the generated asm writer
llvm-svn: 16112
This commit is contained in:
Nate Begeman
parent
b55c0cbaee
commit
143cf94f92
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@ -92,6 +92,12 @@ namespace {
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assert(value <= 31 && "Invalid u5imm argument!");
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O << (unsigned int)value;
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}
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void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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unsigned char value = MI->getOperand(OpNo).getImmedValue();
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assert(value <= 63 && "Invalid u6imm argument!");
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O << (unsigned int)value;
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}
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void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
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@ -427,8 +427,8 @@ class XLForm_2_ext<string name, bits<6> opcode, bits<10> xo, bits<5> bo,
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}
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// 1.7.8 XFX-Form
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class XFXForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: I<name, opcode, ppc64, vmx> {
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class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
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field bits<5> ST;
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field bits<10> SPR;
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@ -443,21 +443,26 @@ class XFXForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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let Inst{11-20} = SPR;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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let OperandList = OL;
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let AsmString = asmstr;
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}
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class XFXForm_1_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
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bit ppc64, bit vmx> : XFXForm_1<name,opcode,xo,ppc64,vmx> {
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class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, bit ppc64,
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bit vmx, dag OL, string asmstr>
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: XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr> {
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let ArgCount = 1;
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let Arg0Type = Gpr.Value;
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let Arg1Type = 0;
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let SPR = spr;
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}
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class XFXForm_7<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: XFXForm_1<name, opcode, xo, ppc64, vmx>;
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class XFXForm_7<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
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class XFXForm_7_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
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bit ppc64, bit vmx> : XFXForm_7<name,opcode,xo,ppc64,vmx> {
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class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
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bit ppc64, bit vmx, dag OL, string asmstr>
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: XFXForm_7<opcode, xo, ppc64, vmx, OL, asmstr> {
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let ArgCount = 1;
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let Arg0Type = Gpr.Value;
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let Arg1Type = 0;
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@ -465,8 +470,8 @@ class XFXForm_7_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
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}
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// 1.7.10 XS-Form
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class XSForm_1<string name, bits<6> opcode, bits<9> xo, bit rc,
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bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
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class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
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field bits<5> RS;
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field bits<5> A;
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field bits<6> SH;
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@ -484,11 +489,13 @@ class XSForm_1<string name, bits<6> opcode, bits<9> xo, bit rc,
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let Inst{21-29} = xo;
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let Inst{30} = SH{0};
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let Inst{31} = rc;
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let OperandList = OL;
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let AsmString = asmstr;
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}
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// 1.7.11 XO-Form
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class XOForm_1<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
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bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
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class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
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field bits<5> RT;
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field bits<5> RA;
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field bits<5> RB;
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@ -506,29 +513,27 @@ class XOForm_1<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
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let Inst{21} = oe;
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let Inst{22-30} = xo;
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let Inst{31} = rc;
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let OperandList = OL;
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let AsmString = asmstr;
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}
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// This is a reversal of the two operands, used notably by extended ops SUB*:
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// sub x, y, z == subf x, z, y
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// subc x, y, z == subfc x, z, y
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class XOForm_1_rev<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
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bit ppc64, bit vmx>
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: XOForm_1<name, opcode, xo, oe, rc, ppc64, vmx> {
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class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
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let Inst{11-15} = RB;
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let Inst{16-20} = RA;
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}
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class XOForm_2<string name, bits<6> opcode, bits<9> xo, bit rc, bit ppc64,
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bit vmx> : XOForm_1<name, opcode, xo, 0, rc, ppc64, vmx>;
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class XOForm_3<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
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bit ppc64, bit vmx> : XOForm_1<name,opcode,xo,oe,rc,ppc64,vmx> {
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class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
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let ArgCount = 2;
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let RB = 0;
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}
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// 1.7.12 A-Form
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class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64,
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bit vmx, dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
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class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
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let ArgCount = 4;
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field bits<5> FRT;
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field bits<5> FRA;
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@ -17,42 +17,24 @@ include "PowerPCInstrFormats.td"
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let isTerminator = 1, isReturn = 1 in
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def BLR : XLForm_2_ext<"blr", 19, 16, 20, 31, 1, 0, 0>;
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class II<dag OL, string asmstr> {
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dag OperandList = OL;
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string AsmString = asmstr;
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}
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def u5imm : Operand<i8> {
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let PrintMethod = "printU5ImmOperand";
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}
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def u6imm : Operand<i8> {
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let PrintMethod = "printU6ImmOperand";
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}
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def u16imm : Operand<i16> {
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let PrintMethod = "printU16ImmOperand";
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}
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// Pseudo-instructions:
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def PHI : Pseudo<"PHI">; // PHI node...
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def PHI : Pseudo<"PHI">;
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def ADJCALLSTACKDOWN : Pseudo<"ADJCALLSTACKDOWN">;
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def ADJCALLSTACKUP : Pseudo<"ADJCALLSTACKUP">;
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<"MovePCtoLR">;
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def IMPLICIT_DEF : Pseudo<"IMPLICIT_DEF">;
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def LA : DForm_2<"la", 14, 0, 0>;
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def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
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def ADDI : DForm_2<"addi", 14, 0, 0>;
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def ADDIS : DForm_2<"addis", 15, 0, 0>;
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def SUBI : DForm_2<"subi", 14, 0, 0>;
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def LI : DForm_2_r0<"li", 14, 0, 0>;
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def LIS : DForm_2_r0<"lis", 15, 0, 0>;
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def ADDIC : DForm_2<"addic", 12, 0, 0>;
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def ADDICo : DForm_2<"addic.", 13, 0, 0>;
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def ADD : XOForm_1<"add", 31, 266, 0, 0, 0, 0>;
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def ADDC : XOForm_1<"addc", 31, 10, 0, 0, 0, 0>;
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def ADDE : XOForm_1<"adde", 31, 138, 0, 0, 0, 0>;
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def ADDZE : XOForm_3<"addze", 31, 202, 0, 0, 0, 0>;
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let isBranch = 1, isTerminator = 1 in {
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def COND_BRANCH : Pseudo<"COND_BRANCH">;
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def B : IForm<"b", 18, 0, 0, 0, 0>;
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@ -77,111 +59,78 @@ let isBranch = 1, isTerminator = 1, isCall = 1,
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def CALLindirect : XLForm_2_ext<"bctrl", 19, 528, 20, 31, 1, 0, 0>;
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}
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def CMPI : DForm_5<"cmpi", 11, 0, 0>;
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def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
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def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
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def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
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def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
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def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
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def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
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def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
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def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
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def DIVW : XOForm_1<"divw", 31, 491, 0, 0, 0, 0>;
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def DIVWU : XOForm_1<"divwu", 31, 459, 0, 0, 0, 0>;
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def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>;
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def LA : DForm_2<"la", 14, 0, 0>;
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def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
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def LBZ : DForm_1<"lbz", 35, 0, 0>;
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def LHA : DForm_1<"lha", 42, 0, 0>;
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def LHZ : DForm_1<"lhz", 40, 0, 0>;
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def LWZ : DForm_1<"lwz", 32, 0, 0>;
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def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
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def LD : DSForm_2<"ld", 58, 0, 1, 0>;
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def LMW : DForm_1<"lmw", 46, 0, 0>;
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def STMW : DForm_3<"stmw", 47, 0, 0>;
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def LFS : DForm_8<"lfs", 48, 0, 0>;
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def LFD : DForm_8<"lfd", 50, 0, 0>;
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def MFLR : XFXForm_1_ext<"", 31, 399, 8, 0, 0>,
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II<(ops GPRC:$reg), "mflr $reg">;
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def MFCTR : XFXForm_1_ext<"mfctr", 31, 399, 9, 0, 0>;
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def MTLR : XFXForm_7_ext<"mtlr", 31, 467, 8, 0, 0>;
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def MTCTR : XFXForm_7_ext<"mtctr", 31, 467, 9, 0, 0>;
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def MULLD : XOForm_1<"mulld", 31, 233, 0, 0, 1, 0>;
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def LWZ : DForm_1<"lwz", 32, 0, 0>;
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def ADDI : DForm_2<"addi", 14, 0, 0>;
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def ADDIC : DForm_2<"addic", 12, 0, 0>;
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def ADDICo : DForm_2<"addic.", 13, 0, 0>;
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def ADDIS : DForm_2<"addis", 15, 0, 0>;
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def MULLI : DForm_2<"mulli", 7, 0, 0>;
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def MULLW : XOForm_1<"mullw", 31, 235, 0, 0, 0, 0>;
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def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>;
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def NEG : XOForm_3<"neg", 31, 104, 0, 0, 0, 0>;
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def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
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def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
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def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
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def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
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def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
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def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
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def SRADI : XSForm_1<"sradi", 31, 413, 0, 1, 0>;
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def SRWI : MForm_2<"srwi", 21, 0, 0, 0>;
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def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
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def SUBI : DForm_2<"subi", 14, 0, 0>;
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def LI : DForm_2_r0<"li", 14, 0, 0>;
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def LIS : DForm_2_r0<"lis", 15, 0, 0>;
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def STMW : DForm_3<"stmw", 47, 0, 0>;
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def STB : DForm_3<"stb", 38, 0, 0>;
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def STBU : DForm_3<"stbu", 39, 0, 0>;
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def STH : DForm_3<"sth", 44, 0, 0>;
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def STHU : DForm_3<"sthu", 45, 0, 0>;
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def STW : DForm_3<"stw", 36, 0, 0>;
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def STWU : DForm_3<"stwu", 37, 0, 0>;
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def STD : DSForm_2<"std", 62, 0, 1, 0>;
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def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
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def CMPI : DForm_5<"cmpi", 11, 0, 0>;
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def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
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def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
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def LFS : DForm_8<"lfs", 48, 0, 0>;
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def LFD : DForm_8<"lfd", 50, 0, 0>;
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def STFS : DForm_9<"stfs", 52, 0, 0>;
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def STFD : DForm_9<"stfd", 54, 0, 0>;
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def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
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def SUB : XOForm_1_rev<"sub", 31, 40, 0, 0, 0, 0>;
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def SUBF : XOForm_1<"subf", 31, 40, 0, 0, 0, 0>;
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def SUBC : XOForm_1_rev<"subc", 31, 8, 0, 0, 0, 0>;
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def SUBFC : XOForm_1<"subfc", 31, 8, 0, 0, 0, 0>;
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def SUBFE : XOForm_1<"subfe", 31, 136, 0, 0, 0, 0>;
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def SUBFZE : XOForm_3<"subfze", 31, 200, 0, 0, 0, 0>;
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def FMADD : AForm_1<63, 29, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fmadd $FRT, $FRA, $FRC, $FRB">;
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def FSEL : AForm_1<63, 23, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fsel $FRT, $FRA, $FRC, $FRB">;
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def FADD : AForm_2<63, 21, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fadd $FRT, $FRA, $FRB">;
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def FADDS : AForm_2<59, 21, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fadds $FRT, $FRA, $FRB">;
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def FDIV : AForm_2<63, 18, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fdiv $FRT, $FRA, $FRB">;
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def FDIVS : AForm_2<59, 18, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fdivs $FRT, $FRA, $FRB">;
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def FMUL : AForm_3<63, 25, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fmul $FRT, $FRA, $FRB">;
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def FMULS : AForm_3<59, 25, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fmuls $FRT, $FRA, $FRB">;
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def FSUB : AForm_2<63, 20, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fsub $FRT, $FRA, $FRB">;
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def FSUBS : AForm_2<59, 20, 0, 0, 0,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fsubs $FRT, $FRA, $FRB">;
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def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
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def LD : DSForm_2<"ld", 58, 0, 1, 0>;
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def STD : DSForm_2<"std", 62, 0, 1, 0>;
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def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
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def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
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def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
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def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
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def SRWI : MForm_2<"srwi", 21, 0, 0, 0>;
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def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
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def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
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def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
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def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
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def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
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def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
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def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
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def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
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def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>;
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// D-Form instructions. Most instructions that perform an operation on a
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// register and an immediate are of this type.
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//
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def ANDIo : DForm_4<28, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2">;
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def ORI : DForm_4<24, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"ori $dst, $src1, $src2">;
|
||||
def ORIS : DForm_4<25, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"oris $dst, $src1, $src2">;
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"andi. $dst, $src1, $src2">;
|
||||
def ORI : DForm_4<24, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"ori $dst, $src1, $src2">;
|
||||
def ORIS : DForm_4<25, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"oris $dst, $src1, $src2">;
|
||||
def XORI : DForm_4<26, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"xori $dst, $src1, $src2">;
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"xori $dst, $src1, $src2">;
|
||||
def XORIS : DForm_4<27, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"xoris $dst, $src1, $src2">;
|
||||
def CMPLI : DForm_6<10, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"xoris $dst, $src1, $src2">;
|
||||
def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
|
||||
def CMPLI : DForm_6<10, 0, 0,
|
||||
(ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
|
||||
"cmpli $dst, $size, $src1, $src2">;
|
||||
def CMPLWI : DForm_6_ext<10, 0, 0,
|
||||
|
|
@ -191,6 +140,9 @@ def CMPLDI : DForm_6_ext<10, 1, 0,
|
|||
(ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"cmpldi $dst, $src1, $src2">;
|
||||
|
||||
// X-Form instructions. Most instructions that perform an operation on a
|
||||
// register and another register are of this type.
|
||||
//
|
||||
def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lbzx $dst, $base, $index">;
|
||||
def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
|
|
@ -277,6 +229,8 @@ def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
|
|||
def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
"stfdx $frS, $rA, $rB">;
|
||||
|
||||
// XL-Form instructions. condition register logical ops.
|
||||
//
|
||||
def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
|
||||
"crand $D, $A, $B">;
|
||||
def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
|
||||
|
|
@ -285,3 +239,86 @@ def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
|
|||
"crnor $D, $A, $B">;
|
||||
def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
|
||||
"cror $D, $A, $B">;
|
||||
|
||||
// XFX-Form instructions. Instructions that deal with SPRs
|
||||
//
|
||||
def MFCTR : XFXForm_1_ext<31, 399, 9, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
|
||||
def MFLR : XFXForm_1_ext<31, 399, 8, 0, 0, (ops GPRC:$rT), "mflr $rT">;
|
||||
def MTCTR : XFXForm_7_ext<31, 467, 9, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
|
||||
def MTLR : XFXForm_7_ext<31, 467, 8, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
|
||||
|
||||
|
||||
// XS-Form instructions. Just 'sradi'
|
||||
//
|
||||
def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
|
||||
"sradi $rA, $rS, $SH">;
|
||||
|
||||
// XO-Form instructions. Arithmetic instructions that can set overflow bit
|
||||
//
|
||||
def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"add $rT, $rA, $rB">;
|
||||
def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"addc $rT, $rA, $rB">;
|
||||
def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"adde $rT, $rA, $rB">;
|
||||
def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"divw $rT, $rA, $rB">;
|
||||
def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"divwu $rT, $rA, $rB">;
|
||||
def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"mulhwu $rT, $rA, $rB">;
|
||||
def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"mulld $rT, $rA, $rB">;
|
||||
def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"mullw $rT, $rA, $rB">;
|
||||
def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"subf $rT, $rA, $rB">;
|
||||
def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"subfc $rT, $rA, $rB">;
|
||||
def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"subfe $rT, $rA, $rB">;
|
||||
def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"sub $rT, $rA, $rB">;
|
||||
def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"subc $rT, $rA, $rB">;
|
||||
def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
|
||||
"addze $rT, $rA">;
|
||||
def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
|
||||
"neg $rT, $rA">;
|
||||
def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
|
||||
"subfze $rT, $rA">;
|
||||
|
||||
// A-Form instructions. Most of the instructions executed in the FPU are of
|
||||
// this type.
|
||||
//
|
||||
def FMADD : AForm_1<63, 29, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
||||
"fmadd $FRT, $FRA, $FRC, $FRB">;
|
||||
def FSEL : AForm_1<63, 23, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
||||
"fsel $FRT, $FRA, $FRC, $FRB">;
|
||||
def FADD : AForm_2<63, 21, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
||||
"fadd $FRT, $FRA, $FRB">;
|
||||
def FADDS : AForm_2<59, 21, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
||||
"fadds $FRT, $FRA, $FRB">;
|
||||
def FDIV : AForm_2<63, 18, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
||||
"fdiv $FRT, $FRA, $FRB">;
|
||||
def FDIVS : AForm_2<59, 18, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
||||
"fdivs $FRT, $FRA, $FRB">;
|
||||
def FMUL : AForm_3<63, 25, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
||||
"fmul $FRT, $FRA, $FRB">;
|
||||
def FMULS : AForm_3<59, 25, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
||||
"fmuls $FRT, $FRA, $FRB">;
|
||||
def FSUB : AForm_2<63, 20, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
||||
"fsub $FRT, $FRA, $FRB">;
|
||||
def FSUBS : AForm_2<59, 20, 0, 0, 0,
|
||||
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
||||
"fsubs $FRT, $FRA, $FRB">;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue