Convert regclass alignment from bytes to bites

llvm-svn: 15972
2004-08-21 20:13:09 +00:00 · 2004-08-21 20:13:09 +00:00 · a440d5b081
parent b7ddc73b45
commit a440d5b081
1 changed files with 1 additions and 1 deletions
--- a/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
+++ b/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
@ -35,7 +35,7 @@ let Namespace = "SparcV9" in {
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
+def IntRegs : RegisterClass<i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
                                     O0, O1, O2, O3, O4, O5, O6, O7,
                                     L0, L1, L2, L3, L4, L5, L6, L7,
                                     I0, I1, I2, I3, I4, I5, I6, I7]>;