2019-10-01 01:03:21 +08:00
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# See LICENSE for license details.
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2023-01-18 19:33:41 +08:00
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# Defines make targets for:
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# - invoking Golden Gate (phony: verilog / compile)
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# - building a simulation driver (phony: f1)
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# - populating an FPGA build directory (phony: replace-rtl)
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# - generating new runtime configurations (phony: conf)
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2023-05-26 07:49:47 +08:00
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# - compiling meta-simulators (phony: verilator, vcs, verilator-debug, vcs-debug, xcelium)
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2023-01-18 19:33:41 +08:00
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2023-03-30 20:39:53 +08:00
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# ensure make is not executed in parallel (ignore -j)
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.NOTPARALLEL:
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2023-01-06 21:54:34 +08:00
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.PHONY: default
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default: compile
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2019-05-28 06:49:44 +08:00
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ifndef FIRESIM_ENV_SOURCED
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$(error You must source sourceme-f1-manager.sh or env.sh to use this Makefile)
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endif
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firesim_base_dir := $(abspath .)
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2023-01-06 21:54:34 +08:00
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# Set up environment variables pointing to Chipyard and SBT.
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include make/chipyard.mk
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2019-05-28 06:49:44 +08:00
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2018-05-14 03:40:34 +08:00
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##################
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# Parameters #
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##################
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2021-07-03 07:13:38 +08:00
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# Multiple target-projects, each with their own chisel generator, co-exist in firesim.
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2018-08-27 11:22:37 +08:00
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# Their sources exist in:
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# src/main/{cc, scala, makefrag}/<target-project-name>
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2018-08-08 12:51:24 +08:00
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#
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# Currently these projects are:
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2021-07-03 07:13:38 +08:00
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# firesim: the default, Chipyard-based target-designs
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# midasexamples: simple chisel designs demonstrating FireSim's features
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2018-08-27 11:22:37 +08:00
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TARGET_PROJECT ?= firesim
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2018-05-14 03:40:34 +08:00
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2023-01-18 19:33:41 +08:00
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# Users can override this to point at a collections of Makefrags.
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# The following makefrags must be present in the folder:
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# config.mk: override configuration variables with project specifics
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# build.mk: define the build rule generating the input FIRRTL and annotations
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# driver.mk: define the configuration for the driver
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# metasim.mk: define rules to run metasimulator binaries.
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TARGET_PROJECT_MAKEFRAG ?= $(firesim_base_dir)/src/main/makefrag/$(TARGET_PROJECT)
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2018-08-26 03:49:11 +08:00
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2022-06-15 14:38:01 +08:00
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# The host-platform type (currently only f1, vitis supported)
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PLATFORM ?= f1
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2019-05-28 06:49:44 +08:00
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2023-01-06 21:54:34 +08:00
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####################
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# Target Setup #
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####################
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2018-08-27 11:22:37 +08:00
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2023-01-18 19:33:41 +08:00
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include $(TARGET_PROJECT_MAKEFRAG)/config.mk
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2023-01-06 21:54:34 +08:00
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include make/config.mk
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2023-01-20 06:12:49 +08:00
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include make/scala-build.mk
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2023-01-18 19:33:41 +08:00
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include $(TARGET_PROJECT_MAKEFRAG)/build.mk
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2023-01-06 21:54:34 +08:00
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include make/goldengate.mk
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2023-02-24 14:06:50 +08:00
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include make/post-synth.mk
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2023-01-18 19:33:41 +08:00
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include $(TARGET_PROJECT_MAKEFRAG)/driver.mk
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include make/library.mk
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2023-01-06 21:54:34 +08:00
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include make/driver.mk
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2023-01-13 05:09:13 +08:00
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include make/fpga.mk
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2023-05-26 07:49:47 +08:00
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2023-01-18 19:33:41 +08:00
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include make/verilator.mk
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include make/vcs.mk
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2023-05-26 07:49:47 +08:00
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include make/xcelium.mk
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2023-01-13 05:09:13 +08:00
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include make/xsim.mk
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2023-01-18 19:33:41 +08:00
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include $(TARGET_PROJECT_MAKEFRAG)/metasim.mk
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2023-01-06 21:54:34 +08:00
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include make/unittest.mk
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2023-01-25 00:42:20 +08:00
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include make/scala-lint.mk
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include make/cpp-lint.mk
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2023-01-06 21:54:34 +08:00
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#########################
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# Cleaning Recipes #
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#########################
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.PHONY: mostlyclean
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mostlyclean:
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2023-05-26 07:49:47 +08:00
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rm -rf $(verilator) $(verilator_debug) $(vcs) $(vcs_debug) $(xcelium) $($(PLATFORM)) $(OUTPUT_DIR)
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2023-01-06 21:54:34 +08:00
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.PHONY: clean
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clean:
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rm -rf $(GENERATED_DIR) $(OUTPUT_DIR)
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.PHONY: veryclean
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veryclean:
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rm -rf generated-src output
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# Remove all implicit suffix rules; This improves make performance substantially as it no longer
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# attempts to resolve implicit rules on 1000+ scala files.
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.SUFFIXES:
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